Commit Graph

105 Commits

Author SHA1 Message Date
Kazu Hirata
76af93fbea Partially revert "[TableGen] Avoid repeated hash lookups (NFC) (#122586)"
This partially reverts commit 07ff786e39.

The hunk being reverted in this patch seems to break:

  tools/llvm-gsymutil/ARM_AArch64/macho-merged-funcs-dwarf.yaml

under LLVM_ENABLE_EXPENSIVE_CHECKS.
2025-01-12 23:50:58 -08:00
Kazu Hirata
07ff786e39 [TableGen] Avoid repeated hash lookups (NFC) (#122586) 2025-01-11 13:15:30 -08:00
Evgenii Kudriashov
2bbdce9a42 [GlobalISel] Support physical register inputs in nested patterns (#121239)
When importing nested patterns, we create InsnMatcher for each pattern
and miss them if consider only the top level InsnMatcher. Iterate
PhysRegOperands instead.

Change the type of PhysRegOperands from DenseMap to SmallMapVector to
have stable generation. Also drop PhysRegInputs member from InsnMatcher
as there are no users of it.
2025-01-05 01:10:25 +01:00
Sergei Barannikov
a7cd660bd7 [TableGen][GISel] Learn to import patterns with optional defs (#120470)
The number of skipped patterns reduces for ARM from 4278 to 4257.
This is the only in-tree target that makes use of OptionalDefOperand.

Pull Request: https://github.com/llvm/llvm-project/pull/120470
2024-12-21 05:24:57 +03:00
Kazu Hirata
0575815b70 [TableGen] Avoid repeated hash lookups (NFC) (#120681) 2024-12-20 10:28:58 -08:00
Kazu Hirata
5b5b241edf [TableGen] Avoid repeated hash lookups (NFC) (#120619) 2024-12-19 13:02:55 -08:00
Kazu Hirata
b0a4b5b35a [TableGen] Avoid repeated hash lookups (NFC) (#120532) 2024-12-19 08:00:02 -08:00
Sergei Barannikov
73eecb70c2 [TableGen][GISel] Don't use std::optional with pointers (NFC) (#120026)
Pointers already have a well-defined null value.
2024-12-16 04:45:06 +03:00
Sergei Barannikov
97c3c32372 [TableGen][SystemZ] Correctly check the range of a leaf immediate (#119931)
The "Size >= 32" check probably dates back to when TableGen integers
were 32-bit. Delete it and simplify code by using `isInt`/`isUInt`.
2024-12-14 13:58:23 +03:00
Sergei Barannikov
d1f51c67fd [TableGen] Add TreePatternNode::children and use it in for loops (NFC) (#119877) 2024-12-13 22:05:57 +03:00
Sergei Barannikov
6b2232606d [TableGen] Replace WantRoot/WantParent SDNode properties with flags (#119599)
These properties are only valid on ComplexPatterns. Having them as flags
is more convenient because one can now use "let = ... in" syntax to set
these flags on several patterns at a time. This is also less error-prone
as it makes it impossible to specify these properties on records derived
from SDPatternOperator.

Pull Request: https://github.com/llvm/llvm-project/pull/119599
2024-12-12 00:41:44 +03:00
abhishek-kaushik22
31ce47b5d6 [TableGen] Use std::move to avoid copy (#113061) 2024-11-21 11:48:46 -08:00
Yingwei Zheng
c727b48287 [SDAG][ISel][TableGen][LoongArch] Report error for trivial bitcasts when there are predicate calls (#116075)
On loongarch64 with lsx extension, we select `VBITREV_W` for `v4i32 (xor
X, (shl splat(1), Y))`:

8e66303916/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td (L1583-L1584)

And `vsplat_imm_eq_1` is defined as:

8e66303916/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td (L77-L87)

For the `(bitconvert (v4i32 (build_vector)))` case, the pattern is
expected to be:
```
PATTERN: (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vj, (shl:{ *:[v4i32] } (bitconvert:{ *:[v4i32] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplat_imm_eq_1>>, v4i32:{ *:[v4i32] }:$vk))
RESULT:  (VBITREV_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vj, v4i32:{ *:[v4i32] }:$vk)
```

However, `simplifyTree` drops the `bitconvert` node and its predicates:

8e66303916/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp (L3036-L3062)

Then llvm will match `vsplat_imm_eq_1` for any v4i32 splats and cause a
miscompilation:
```
PATTERN: (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vj, (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vk))
RESULT:  (VBITREV_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vj, v4i32:{ *:[v4i32] }:$vk)
```

This patch adds additional checks for predicates associated with the
trivial bitconvert node. Unused patterns in the LoongArch target are
also removed.

Fixes https://github.com/llvm/llvm-project/issues/116008.
2024-11-19 21:24:40 +08:00
Craig Topper
92ffefe351 [Tablegen] Add more comments for result numbers to DAGISelEmitter.cpp (#116533)
Print what result number the Emit* nodes are storing their results in.
This makes it easy to track the inputs of later opcodes that consume
these results.
2024-11-17 19:11:28 -08:00
Kazu Hirata
4048c64306 [llvm] Remove redundant control flow statements (NFC) (#115831)
Identified with readability-redundant-control-flow.
2024-11-12 10:09:42 -08:00
Sergei Barannikov
501a583441 [TableGen][SelectionDAG] Remove the implicit DAG node (#115295)
The node was introduced in 59c39dc1 and was intended to allow writing
patterns like this:
`[(set AL, (mul AL, GR8:$src1)), (implicit EFLAGS)]`

However, it does not introduce new functionality because the same
pattern can be equivalently expressed as:
`[(set AL, EFLAGS, (mul AL, GR8:$src1))]`

The latter form is also more flexible as it allows reordering output
operands.

In most places uses of `implicit` were redundant -- removing them didn't
change anything in the generated DAG tables. The only three cases where
it did have effect are in X86InstrArithmetic.td and X86InstrSystem.td --
those were rewritten to use `set` node.

Removing `implicit` from some patterns made them importable by GISel,
hence the change in a test.
2024-11-09 07:25:40 +03:00
Sander de Smalen
ae0ab24862 [TableGen] Fix calculation of Lanemask for RCs with artificial subregs. (#114392)
TableGen builds up a map of "SubRegIdx -> Subclass" where Subclass is
the largest class where all registers have SubRegIdx as a sub-register.
When SubRegIdx (vis-a-vis the sub-register) is artificial it should
still include it in the map. This map is used in various places,
including in the calculation of the Lanemask of a register class, which
otherwise calculates an incorrect lanemask.
2024-11-04 16:10:50 +00:00
Sander de Smalen
9a211fe7e4 [TableGen] Fix concatenation of subreg and artificial subregs (#114391)
When CoveredBySubRegs is true and a sub-register consists of two
parts; a regular subreg and an artificial subreg, then TableGen
should consider only concatenating the non-artificial subregs. 
For example, S0_S1 is a concatenated subreg from D0_D1,
but S0_S1_HI should not be considered.
2024-11-04 15:51:19 +00:00
abhishek-kaushik22
a58c3d3ac7 Use std::move to avoid copy (#113055) 2024-11-04 07:28:00 -08:00
Fangrui Song
9bb5af8a42 [TableGen] Replace StringRef::slice with substr. NFC 2024-10-30 22:27:12 -07:00
Jessica Clarke
9467645547 [CodeGen] Rename MVT::iPTRAny to MVT::pAny
Whilst in upstream LLVM iPTRAny is only ever an integer, essentially an
alias for iPTR, this is not true in CHERI LLVM, where it gets used to
mean "iPTR or cPTR", i.e. either an integer address or a capability
(with cPTR and cN being the capability equivalents of iPTR and iN).
Moreover, iPTRAny is already not itself regarded as an integer (calling
isInteger() will give false), so the "i" prefix is misleading, and it
stands out as different from all the other xAny that have a single
letter prefix denoting their type.

Thus, rename it to pAny, reflecting that it is an overloaded pointer
type, which could end up being specialised to an integer type, but does
not have to be.

This has been verified to have no effect on the generated files for LLVM
itself or any in-tree target beyond the replacement of the identifier
iPTRAny with pAny in GenVT.inc.

Reviewers: arsenm

Reviewed By: arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/113733
2024-10-30 03:27:48 +00:00
Jessica Clarke
e8b7f53fa4 [TableGen] Remove a pointless check for iPTRAny
We've already called EnforceInteger on Types[0], and iPTRAny isn't
regarded as an integer type (note that TableGen special-cases iPTR here
to include that, though), so we cannot possibly still have an iPTRAny by
this point. Delete the check, and let getFixedSizeInBits catch it along
with all the other overloaded types if that ever becomes false. Also
document why we have this check whilst here.

Reviewers: arsenm

Reviewed By: arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/113732
2024-10-30 03:19:53 +00:00
Jessica Clarke
ef455e6b16 [TableGen] Replace all lingering uses of getName with getEnumName
The former is a wrapper for the latter with two differences: Other is
mapped to "UNKNOWN" (rather than "MVT::Other"), and iPTR(Any) are mapped
to "TLI.getPointerTy()" rather than "MVT::iPTR(Any)".

The only uses are in FastISelMap::printFunctionDefinitions. Most of
these uses are just a form of name mangling to ensure uniqueness, so the
actual string isn't important (and, in the case of MVT::iPTR(Any), were
both to be used, they would clash). Two uses are for a case statement,
which requires the expression to be a constant (of the right type), but
neither UNKNOWN nor TLI.getPointerTy() are constants, so would not work
there. The remaining uses are where an expression is needed, so UNKNOWN
similarly doesn't work, though TLI.getPointerTy() could in this case.
However, neither iPTR nor iPTRAny are supposed to make it this far
through TableGen, and should instead have been replaced with concrete
types, so this case should not be hit. Moreover, for almost all of these
uses, the name is passed to getLegalCName, which will strip an MVT::
prefix but will leave TLI.getPointerTy() unchanged, which is not a valid
C identifier, nor component thereof.

Thus, delete this unnecessary, and mostly-broken, wrapper and just use
the underlying getEnumName. This has been verified to have no effect on
the generated files for any in-tree target, including experimental ones.

Reviewers: arsenm

Reviewed By: arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/113731
2024-10-30 03:12:23 +00:00
Rahul Joshi
743f839a88 [NFC][LLVM][TableGen] Change RecordKeeper::getClass to return const pointer (#112261)
Change `RecordKeeper::getClass` to return const record pointer. This is
a part of effort to have better const correctness in TableGen backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-10-23 11:32:05 -07:00
Rahul Joshi
62e2c7fb2d [LLVM][TableGen] Change all Init pointers to const (#112705)
This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-10-18 07:50:22 -07:00
Rahul Joshi
667815ccf4 [NFC][TableGen] Change RecordKeeper::getDef() to return const pointer (#110992)
This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-10-03 08:18:43 -07:00
Rahul Joshi
65e69f7436 [NFC][TableGen] Change Record::getSuperClasses to use const Record* (#110845)
Change `Record::getSuperClasses` to return a const pointer to the
superclass records.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-10-02 13:24:46 -07:00
Rahul Joshi
d256b9e88b [TableGen] Change DefInit::Def to a const Record pointer (#110747)
This change undoes a const_cast<> introduced in an earlier change to
help transition to const pointers. It is a part of effort to have better
const correctness in TableGen backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-10-02 09:48:26 -07:00
Matt Arsenault
37e717ec13 TableGen/GlobalISel: Fix using wrong type for instruction flags
09515f2c20 increased the size of the
MachineInstr flags from uint16_t to uint32_t, so change TableGen
to match.
2024-10-02 12:37:41 +04:00
Rahul Joshi
a140931be5 [TableGen] Change getValueAsListOfDefs to return const pointer vector (#110713)
Change `getValueAsListOfDefs` to return a vector of const Record
pointer, and remove `getValueAsListOfConstDefs` that was added as a
transition aid.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-10-01 14:30:38 -07:00
Rahul Joshi
9d95e2614e [TableGen] Change all type pointers to const (#110602)
This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-10-01 06:54:17 -07:00
Stephen Chou
ec61311e77 [LLVM][TableGen] Support type casts of nodes with multiple results (#109728)
Currently, type casts can only be used to pattern match for intrinsics
with a single overloaded return value. For instance:
```
def int_foo : Intrinsic<[llvm_anyint_ty], []>;
def : Pat<(i32 (int_foo)), ...>;
```

This patch extends type casts to support matching intrinsics with
multiple overloaded return values. As an example, the following defines
a pattern that matches only if the overloaded intrinsic call returns an
`i16` for the first result and an `i32` for the second result:
```
def int_bar : Intrinsic<[llvm_anyint_ty, llvm_anyint_ty], []>;
def : Pat<([i16, i32] (int_bar)), ...>;
```
2024-10-01 11:17:00 +04:00
Rahul Joshi
bfa8519bbb [LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109)
Change GlobalISelEmitter to use const RecordKeeper.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
Rahul Joshi
c92137e474 [NFC][TableGen] Adopt scaled indent in PredicateExpander (#109801)
Adopt scaled indent in PredicateExpander.
Added pre/post inc/dec operators to `indent` and related unit tests.
Verified by comparing *.inc files generated by LLVM build with/without
the change.
2024-09-24 22:05:51 -07:00
Rahul Joshi
3138eb500c [LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467)
Use const record pointers in TableGen/Common files.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
Craig Topper
eb8d865c44 [TableGen] Change getReg() == 0 to !getReg().isValid() in expandCheckInvalidRegOperand. NFC 2024-09-21 22:37:28 -07:00
Rahul Joshi
708567ab0b [LLVM][TableGen] Adopt indent for indentation (#109275)
Adopt `indent` for indentation DAGISelMatcher and DecoderEmitter.
2024-09-20 04:28:01 -07:00
Rahul Joshi
2b01452c20 [LLVM][TableGen] Use const Record pointers in PredicateExpander (#109365)
Use const Record pointers in PredicateExpander.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-20 04:23:52 -07:00
Rahul Joshi
d109636c2e [LLVM][TableGen] Change GISelCombinerEmitter to use const RecordKeeper (#109187)
Change GISelCombinerEmitter to use const RecordKeeper.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-20 04:23:11 -07:00
Rahul Joshi
3e24dd42dd [NFC] Rename variables to conform to LLVM coding standards (#109166)
Rename `indent` to `Indent` and `o` to `OS`.
Rename `Indentation` to `Indent`.
Remove unused argument from `emitPredicateMatch`.
Change `Indent` argument to `emitBinaryParser` to by value.
2024-09-19 04:49:12 -07:00
Rahul Joshi
23123aa4ec [LLVM][TableGen] Change InstrInfoEmitter to use const RecordKeeper (#109189)
Change InstrInfoEmitter to use const RecordKeeper.

This is a part of effort to have better const correctness in TableGen backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-18 22:27:26 -07:00
Rahul Joshi
c29dfb3346 [LLVM][TableGen] Change CodeGenSchedule to use const Record pointers (#108782)
Change CodeGenSchedule to use const Record pointers.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-18 04:45:49 -07:00
Rahul Joshi
100b34bbc1 [LLVM][TableGen] Change VarLenCodeEmitterGen to use const RecordKeeper (#108960)
Change VarLenCodeEmitterGen to use const RecordKeeper.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-17 09:01:04 -07:00
Rahul Joshi
8e00afcfdd [LLVM][TableGen] Change SubtargetEmitter to use const RecordKeeper (#108763)
Change SubtargetEmitter to use const RecordKeeper.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-15 10:26:27 -07:00
Rahul Joshi
87e8b53009 [LLVM][TableGen] Change CodeGenDAGPatterns to use const RecordKeeper (#108762)
Change CodeGenDAGPatterns to use const RecordKeeper.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-15 10:26:03 -07:00
Rahul Joshi
43f044ba7e [LLVM][TableGen] Change CodeGenTarget to use const RecordKeeper (#108752)
Change CodeGenTarget to use const RecordKeeper.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-15 07:33:48 -07:00
Rahul Joshi
8783bd5faa [LLVM][TableGen] Change CodeGenInstAlias to use const Record pointers (#108753)
Change CodeGenInstAlias to use const Record pointers.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-15 07:27:41 -07:00
Rahul Joshi
3ae71d154e [LLVM][TableGen] Change CodeGenSchedule to use const RecordKeeper (#108617)
Change CodeGenSchedule to use const RecordKeeper.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-15 04:55:29 -07:00
Rahul Joshi
d3cdf0f222 [LLVM][Option] Refactor option name comparison (#108219)
Move common functions shared by TableGen Option Emitter
and Options library to Support:
- Move `StrCmpOptionName` and base it on the existing version
  in OptTable.cpp, with an additional mode to control fall back to
  case insensitive comparison.
- Add `StrCmpOptionPrefixes` to compare prefixes and use zip() to
  iterate through lists of prefixes.
- Rename `CompareOptionRecords` to less ambiguous name 
  `IsOptionRecordLess`.
- Merge 2 back-to-back ifs with same condition in
  `IsOptionRecordLess`.

Fixes https://github.com/llvm/llvm-project/issues/107723
2024-09-13 17:30:19 -07:00
Rahul Joshi
7c6592f5a3 [TableGen] Change CodeGenRegister to use const Record pointer (#108027)
Change CodeGenRegister to use const Record pointer.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-11 08:53:47 -07:00