MIPS ABI has relocations like R_MIPS_JALR which is just a hint for
linker to make some code optimization. Such relocations should not be
handled as a regular ones and lead to say dynamic relocation creation.
The patch introduces new virtual `Target::isHintReloc` method, overrides
it in the `MipsTargetInfo` class and calls it in the `Writer<ELFT>::scanRelocs`
method.
Differential Revision: http://reviews.llvm.org/D16193
llvm-svn: 257798
Fix: Added missed input file.
Initial commit message:
[ELF/AArch64] - Implemented R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 and R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC relocations
* R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 is calculated as Page(G(GTPREL(S+A))) – Page(P), set an ADRP immediate field to bits [32:12] of X; check –2^32 ≤ X < 2^32;
* R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC is calculated as G(GTPREL(S+A)), set an LD offset field to bits [11:3] of X. No overflow check; check that X&7 = 0.
Differential revision: http://reviews.llvm.org/D16117
llvm-svn: 257596
* R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 is calculated as Page(G(GTPREL(S+A))) – Page(P), set an ADRP immediate field to bits [32:12] of X; check –2^32 ≤ X < 2^32;
* R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC is calculated as G(GTPREL(S+A)), set an LD offset field to bits [11:3] of X. No overflow check; check that X&7 = 0.
Differential revision: http://reviews.llvm.org/D16117
llvm-svn: 257588
R_AARCH64_TSTBR14 is calculated as S+A-P,
Set the immediate field of a TBZ/TBNZ instruction to bits [15:2] of X; check -2^15 ≤ X < 2^15
Differential revision: http://reviews.llvm.org/D15824
llvm-svn: 257334
R_AARCH64_CONDBR19 is calculated as S+A-P,
Set the immediate field of a conditional branch instruction to bits [20:2] of X; check -2^20 ≤ X< 2^20.
Afaik there is no document for AARCH64 instruction encoding from official for unknown reason, so
I used gold source code and next link as a reference for implementation: http://kitoslab-eng.blogspot.ru/2012/10/armv8-aarch64-instruction-encoding.html. From which is clear that immediate field of a conditional branch instruction is 5 bits off. That is proved by output which is is equal to gold/bfd now.
Differential revision: http://reviews.llvm.org/D15809
llvm-svn: 257333
R_X86_64_PLT32 is handled in the same way as R_X86_64_PC32 by
relocateOne(), so this function does not seems to be needed.
Without this code, all tests still pass.
http://reviews.llvm.org/D15971
llvm-svn: 257203
All non-trivial relocation decisions need explanations like this
to help readers understand not only how relocations are handled but
why they are handled these ways. This is a start.
llvm-svn: 257119
Summary: This will allow us to remove the AMDGPU support from old ELF.
Reviewers: rafael, ruiu
Differential Revision: http://reviews.llvm.org/D15895
llvm-svn: 257023
The R_MIPS_GPREL16 / R_MIPS_GPREL32 relocations use the following
expressions for calculations:
```
local symbol: S + A + GP0 - GP
global symbol: S + A - GP
GP - Represents the final gp value, i.e. _gp symbol
GP0 - Represents the gp value used to create the relocatable object
```
The GP0 value is taken from the .reginfo data section defined by an object
file. To implement that I keep a reference to `MipsReginfoInputSection`
in the `ObjectFile` class. This reference is used by the
`ObjectFile::getMipsGp0` method to return the GP0 value.
Differential Revision: http://reviews.llvm.org/D15760
llvm-svn: 256416
The patch adds support for R_MIPS_PC16, R_MIPS_PC19_S2, R_MIPS_PC21_S2,
R_MIPS_PC26_S2, R_MIPS_PCHI16, R_MIPS_PCLO16 relocations handling.
llvm-svn: 256172
This relocation is similar to R_*_RELATIVE except that the value used in this relocation is the program address returned by the function, which takes no arguments, at the address of
the result of the corresponding R_*_RELATIVE relocation as specified in the processor-specific ABI. The purpose of this relocation to avoid name lookup for locally defined STT_GNU_IFUNC symbols at load-time.
More info can be found in ifunc.txt from https://sites.google.com/site/x32abi/documents.
Differential revision: http://reviews.llvm.org/D15235
llvm-svn: 256144
R_386_GOTOFF is calculated as S + A - GOT, where:
S - Represents the value of the symbol whose index resides in the relocation entry.
A - Represents the addend used to compute the value of the relocatable field.
GOT - Represents the address of the global offset table.
Differential revision: http://reviews.llvm.org/D15383
llvm-svn: 256143
@indntpoff is similar to @gotntpoff, but for use in position dependent code. While @gotntpoff resolves to GOT slot address relative to the
start of the GOT in the movl or addl instructions, @indntpoff resolves to the
absolute GOT slot address. ("ELF Handling For Thread-Local Storage", Ulrich Drepper).
Differential revision: http://reviews.llvm.org/D15494
llvm-svn: 255884
The `R_MIPS_JALR` is a relocation generated by gcc and gas. This
relocation points to the `jalr` instruction which might be optimized and
converted to the `b` instruction under some conditions.
Now we just ignore this relocation and keep instructions unchanged.
llvm-svn: 255453
R_X86_64_SIZE64/R_X86_64_SIZE32 relocations were introduced in 0.98v of "System V Application Binary Interface x86-64" (http://www.x86-64.org/documentation/abi.pdf).
Calculation for them is Z + A, where:
Z - Represents the size of the symbol whose index resides in the relocation entry.
A - Represents the addend used to compute the value of the relocatable field.
Differential revision: http://reviews.llvm.org/D15335
llvm-svn: 255332
If R_386_PLT32 relocation is applied against symbol that can not be preempted then it can be resolved statically.
Patch implements it for x86 target.
Differential revision: http://reviews.llvm.org/D15376
llvm-svn: 255233
Implement the TLS relocation optimization for 32-bit x86 that is described in
"ELF Handling For Thread-Local Storage" by Ulrich Drepper, chapter 5,
"IA-32 Linker Optimizations". Specifically, this patch implements these
optimizations: LD->LE, GD->IE, GD->LD, and IE->LE.
Differential revision: http://reviews.llvm.org/D15292
llvm-svn: 255103
All relocations, which cannot be handled by the dynamic linker,
cause a linking error "rebuild with -fPIC".
Differential revision: http://reviews.llvm.org/D15193
llvm-svn: 254840
"Ulrich Drepper, ELF Handling For Thread-Local Storage" (5.5 x86-x64 linker optimizations, http://www.akkadia.org/drepper/tls.pdf) shows how GD can be optimized to IE.
This patch implements the optimization.
Differential revision: http://reviews.llvm.org/D15000
llvm-svn: 254713
Main aim of the patch to introduce basic support for TLS access models for x86 target.
Models using @tlsgd, @tlsldm and @gotntpoff are implemented.
Differential revision: http://reviews.llvm.org/D15060
llvm-svn: 254500
Some MIPS relocations including `R_MIPS_HI16/R_MIPS_LO16` use combined
addends. Such addend is calculated using addends of both paired relocations.
Each `R_MIPS_HI16` relocation is paired with the next `R_MIPS_LO16`
relocation. ABI requires to compute such combined addend in case of REL
relocation record format only.
For details see p. 4-17 at
ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
This patch implements lookup of the next paired relocation suing new
`InputSectionBase::findPairedRelocLocation` method. The primary
disadvantage of this approach is that we put MIPS specific logic into
the common code. The next disadvantage is that we lookup `R_MIPS_LO16`
for each `R_MIPS_HI16` relocation, while in fact multiple `R_MIPS_HI16`
might be paired with the single `R_MIPS_LO16`. From the other side
this way allows us to keep `MipsTargetInfo` class stateless and implement
later relocation handling in parallel.
This patch does not support `R_MIPS_HI16/R_MIPS_LO16` relocations against
`_gp_disp` symbol. In that case the relocations use a special formula for
the calculation. That will be implemented later.
Differential Revision: http://reviews.llvm.org/D15112
llvm-svn: 254461
ABI specifies the allowed range for these relocations as 2^(n-1) <= X < 2^n.
The patch fixes checks and introduces precise tests for these relocations.
Differential revision: http://reviews.llvm.org/D14957
llvm-svn: 254146
Implements @tlsld (LD to LE) and @tlsgd (GD to LE) optimizations.
Patch does not implement the GD->IE case for @tlsgd.
Differential revision: http://reviews.llvm.org/D14870
llvm-svn: 254101
Patch implements lazy relocations for x86.
One of features of x86 is that executable files and shared object files have separate procedure linkage tables. So patch implements both cases.
Detailed information about instructions used can be found in http://docs.oracle.com/cd/E19620-01/805-3050/chapter6-1235/index.html (search: x86: Procedure Linkage Table).
Differential revision: http://reviews.llvm.org/D14955
llvm-svn: 254098
R_MIPS_CALL16 relocation provides the same result as R_MIPS_GOT16
relocation but does not need to check the result on overflow.
Differential Revision: http://reviews.llvm.org/D14916
llvm-svn: 254092
