Commit Graph

30 Commits

Author SHA1 Message Date
Tim Northover
534acbdf73 AArch64/ARM64: print BFM instructions as BFI or BFXIL
The canonical form of the BFM instruction is always one of the more explicit
extract or insert operations, which makes reading output much easier.

llvm-svn: 207752
2014-05-01 12:29:38 +00:00
Bradley Smith
f57d5ca234 [ARM64] Conditionalize CPU specific system registers on subtarget features
llvm-svn: 207742
2014-05-01 10:25:36 +00:00
Tim Northover
a8c577e454 ARM64: print fp immediates without using scientific notation.
llvm-svn: 207669
2014-04-30 16:13:34 +00:00
Tim Northover
d53a671354 AArch64/ARM64: expunge CPSR from the sources
AArch64 does not have a CPSR register in the same way that AArch32 does. Most
of its compiler-relevant roles have been taken over by the more specific NZCV
register (representing just the flags set by normal instructions).

Its system control functions still remain, but are now under the
pseudo-register referred to as "PSTATE". They're accessed via various MRS & MSR
instructions described in the reference manual.

llvm-svn: 207645
2014-04-30 13:14:14 +00:00
Tim Northover
36c93db37a ARM64: remove duplication by templating InstPrinter methods
No functional change, so no tests.

llvm-svn: 207638
2014-04-30 11:43:36 +00:00
Tim Northover
4b2f8a990e ARM64: hexify printing various immediate operands
This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they
accept weird shifts which are more naturally understandable in hex notation).

Also changes BRK/HINT etc, which is probably a neutral change, but easier than
the alternative.

llvm-svn: 207634
2014-04-30 11:19:28 +00:00
Tim Northover
cfd6e66544 ARM64: print canonical syntax for add/sub (imm) instructions.
Since these instructions only accept a 12-bit immediate, possibly shifted left
by 12, the canonical syntax used by the architecture reference manual is "#N {,
lsl #12 }". We should accept an immediate that has already been shifted, (e.g.

Also, print a comment giving the full addend since it can be helpful.

llvm-svn: 207633
2014-04-30 11:19:15 +00:00
Bradley Smith
672df15122 [ARM64] Print preferred aliases for SFBM/UBFM in InstPrinter
llvm-svn: 207219
2014-04-25 10:25:29 +00:00
Craig Topper
062a2baef0 [C++] Use 'nullptr'. Target edition.
llvm-svn: 207197
2014-04-25 05:30:21 +00:00
Tim Northover
79ec019261 AArch64/ARM64: disentangle the "B.CC" and "LDR lit" operands
These can have different relocations in ELF. In particular both:

    b.eq global
    ldr x0, global

are valid, giving different relocations. The only possible way to distinguish
them is via a different fixup, so the operands had to be separated throughout
the backend.

llvm-svn: 207105
2014-04-24 12:12:10 +00:00
Chandler Carruth
84e68b2994 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE
definition below all of the header #include lines, lib/Target/...
edition.

llvm-svn: 206842
2014-04-22 02:41:26 +00:00
Jim Grosbach
0fba6d98fc ARM64: [su]xtw use W regs as inputs, not X regs.
Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing
mode handling.

PR19455 and rdar://16650642

llvm-svn: 206495
2014-04-17 20:47:31 +00:00
NAKAMURA Takumi
d8570e5bc2 Fix abuse of StringRef on ARM64SysReg::MRSMapper::toString(Val, Valid).
FIXME: Could we use SmallString here?
llvm-svn: 205950
2014-04-10 03:05:59 +00:00
Bradley Smith
246b0b617d [ARM64] Change SYS without a register to an alias to make disassembling more consistant.
llvm-svn: 205898
2014-04-09 14:44:58 +00:00
Bradley Smith
2cef19a2e6 [ARM64] Correctly disassemble ISB operand as ISB not DBarrier.
llvm-svn: 205897
2014-04-09 14:44:54 +00:00
Bradley Smith
f280e91849 [ARM64] Conditional branches must always print their condition code, even AL.
llvm-svn: 205894
2014-04-09 14:44:39 +00:00
Bradley Smith
a0d7a9a12f [ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional.
llvm-svn: 205892
2014-04-09 14:44:31 +00:00
Bradley Smith
70c6acbbfd [ARM64] Add missing shifted register MVN alias to ORN
llvm-svn: 205891
2014-04-09 14:44:26 +00:00
Bradley Smith
403bbf95c0 [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.
llvm-svn: 205890
2014-04-09 14:44:22 +00:00
Bradley Smith
779238a216 [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a dumb alias.
llvm-svn: 205889
2014-04-09 14:44:18 +00:00
Bradley Smith
a0dce246ed [ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions.
llvm-svn: 205886
2014-04-09 14:44:03 +00:00
Bradley Smith
9f29b726d5 [ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.
llvm-svn: 205876
2014-04-09 14:43:11 +00:00
Bradley Smith
3339427e2a [ARM64] Remove PrefetchOp and use ARM64PRFM instead.
llvm-svn: 205872
2014-04-09 14:42:53 +00:00
Bradley Smith
fb90df563f [ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS.
llvm-svn: 205869
2014-04-09 14:42:42 +00:00
Bradley Smith
08c391c156 [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process.
llvm-svn: 205868
2014-04-09 14:42:36 +00:00
Bradley Smith
2ba17a4a17 [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent.
llvm-svn: 205867
2014-04-09 14:42:27 +00:00
Tim Northover
adbd34e045 ARM64: format register strings without creating a local Twine.
It was causing horrible failures on some build-bots.

llvm-svn: 205105
2014-03-29 15:35:57 +00:00
Tim Northover
2011df293d ARM64: change format specifier to work on 32-bit targets
Existing tests were failing.

llvm-svn: 205092
2014-03-29 11:47:07 +00:00
Chandler Carruth
7b7a67c5c8 [ARM64] Fix 'assert("...")' to be 'assert(0 && "...")'. Otherwise, it is
no assert at all. ;] Some of these should probably be switched to
llvm_unreachable, but I didn't want to perturb the behavior in this
patch.

Found by -Wstring-conversion, which I'll try to turn on in CMake builds
at least as it is finding useful things.

llvm-svn: 205091
2014-03-29 11:07:40 +00:00
Tim Northover
00ed9964c6 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

llvm-svn: 205090
2014-03-29 10:18:08 +00:00