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86 Commits

Author SHA1 Message Date
Bill Wendling
91607f878c Emit a '!' if this is a "writeback" register or memory address. 
llvm-svn: 118662
 2010-11-10 01:07:54 +00:00
Matt Beaumont-Gay
55c4cc76ce Rename a parameter to avoid confusion with a local variable 
llvm-svn: 118656
 2010-11-10 00:08:58 +00:00
Bill Wendling
e9a9c6da04 Emit the warning about the register list not being in ascending order only once. 
llvm-svn: 118653
 2010-11-09 23:45:59 +00:00
Bill Wendling
bed9465a96 s/std::vector/SmallVector/ 
llvm-svn: 118648
 2010-11-09 23:28:44 +00:00
Bill Wendling
da3c0fbc64 Delete the allocated vector. 
llvm-svn: 118644
 2010-11-09 22:51:42 +00:00
Bill Wendling
2cae3277a5 Two types of instructions have register lists: 
* LDM, et al, uses a bit mask to indicate the register list.
* VLDM, et al, uses a base register plus number.

The LDM instructions may be non-contiguous, but the VLDM ones must be
contiguous. Those are semantic checks that should be done later in the
compiler. Also postpone the creation of the bit mask until it's needed.

llvm-svn: 118640
 2010-11-09 22:44:22 +00:00
Bill Wendling
8d2aa03ce1 The "addRegListOperands()" function returns the start register and the total 
number of registers in the list.

llvm-svn: 118456
 2010-11-08 23:49:57 +00:00
Bill Wendling
2f9d17c44f Revert. 
llvm-svn: 118389
 2010-11-08 00:32:40 +00:00
Bill Wendling
68bac75190 In this context, a reglist is a reg. 
llvm-svn: 118375
 2010-11-07 13:08:28 +00:00
Bill Wendling
e18980aeaa Add support for parsing register lists. We can't use a bitfield to keep track of 
the registers, because the register numbers may be much greater than the number
of bits available in the machine's register.

I extracted the register list verification code out of the actual parsing of the
registers. This made checking for errors much easier. It also limits the number
of warnings that would be emitted for cascading infractions.

llvm-svn: 118363
 2010-11-06 22:36:58 +00:00
Bill Wendling
b884a8ee44 Return the base register of a register list for the "getReg()" method. This is 
to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.

llvm-svn: 118360
 2010-11-06 22:19:43 +00:00
Bill Wendling
ee7f1f9914 General cleanup: 
- Make ARMOperand a class so that some things are internal to the class.
- Reformatting.

llvm-svn: 118357
 2010-11-06 21:42:12 +00:00
Bill Wendling
7cef447c14 Add a RegList (register list) object to ARMOperand. It will be used soon to hold 
(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.

llvm-svn: 118351
 2010-11-06 19:56:04 +00:00
Bill Wendling
8300d834c9 Fix grammar. 
llvm-svn: 118341
 2010-11-06 10:51:53 +00:00
Bill Wendling
4f4bce0682 Fix grammar. 
llvm-svn: 118340
 2010-11-06 10:48:18 +00:00
Bill Wendling
518e43c453 MatchRegisterName() returns 0 if it can't match the register. 
llvm-svn: 118339
 2010-11-06 10:45:34 +00:00
Bill Wendling
6d2eb737af Use TryParseRegister() instead of MatchRegisterName(). The former returns -1 
while the latter doesn't.

llvm-svn: 118338
 2010-11-06 10:40:24 +00:00
Jim Grosbach
2db0ea03ba Hook up the '.code {16|32}' directive to the streamer. 
llvm-svn: 118310
 2010-11-05 22:40:53 +00:00
Jim Grosbach
c6db8ce5da Hook up the '.thumb_func' directive to the streamer. 
llvm-svn: 118307
 2010-11-05 22:33:53 +00:00
Jim Grosbach
0fe92e3fea Fix past-o. 
llvm-svn: 118304
 2010-11-05 22:11:33 +00:00
Bill Wendling
e84eb99cbb The MC code couldn't handle ARM LDR instructions with negative offsets: 
vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.

llvm-svn: 118144
 2010-11-03 01:49:29 +00:00
Jim Grosbach
7d45c101e5 Add FIXME. 
llvm-svn: 117936
 2010-11-01 18:11:14 +00:00
Jim Grosbach
0190a649e8 Mark ARM subtarget features that are available for the assembler. 
llvm-svn: 117929
 2010-11-01 16:59:54 +00:00
Jim Grosbach
99710a871c trailing whitespace 
llvm-svn: 117927
 2010-11-01 16:44:21 +00:00
Jim Grosbach
a71c9e2ebf Tidy up. 
llvm-svn: 117782
 2010-10-30 12:59:16 +00:00
Chris Lattner
549a31cd34 simplify this code. 
llvm-svn: 117771
 2010-10-30 04:35:59 +00:00
Chris Lattner
44e5981c1b split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic. 
llvm-svn: 117769
 2010-10-30 04:09:10 +00:00
Bill Wendling
193961bb1a Some instructions end with an "ls" prefix, but it doesn't indicate that they are 
conditional. Check for those instructions explicitly.

llvm-svn: 117747
 2010-10-29 23:50:21 +00:00
Jim Grosbach
31f23b48ba add FIXME 
llvm-svn: 117718
 2010-10-29 21:56:51 +00:00
Jim Grosbach
16bd9f1ab5 Handle ARM addrmode5 instructions with an offset. 
llvm-svn: 117672
 2010-10-29 17:41:25 +00:00
Jim Grosbach
305ec65927 Revert 117660. Apparently it's not as trivial as that... 
llvm-svn: 117663
 2010-10-29 16:50:53 +00:00
Jim Grosbach
8682b69b81 ARM addrmode5 instructions have neither writeback nor post-indexed modes. 
llvm-svn: 117660
 2010-10-29 16:38:59 +00:00
Jim Grosbach
624bcc7371 Trailing whitespace. 
llvm-svn: 117651
 2010-10-29 14:46:02 +00:00
Benjamin Kramer
08b8c534f7 ARMAsmParser: Plug a memory leak. 
llvm-svn: 117648
 2010-10-29 09:43:39 +00:00
Eric Christopher
91d7b90185 Add an unreachable to silence warning - the switch is actually 
fully enumerated.

llvm-svn: 117647
 2010-10-29 09:26:59 +00:00
Chris Lattner
5d6f6a061b add simple support for addrmode5 operands, allowing 
vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.

llvm-svn: 117626
 2010-10-29 00:27:31 +00:00
Chris Lattner
d27b05e54a give better error diagnostics, for example: 
t.s:1:14: error: invalid operand for instruction
vldr.64	d17, [r0]   
       	     ^

instead of:

t.s:1:1: error: unrecognized instruction
vldr.64	d17, [r0]   
^

llvm-svn: 117611
 2010-10-28 21:41:58 +00:00
Chris Lattner
9487de6160 move a method out of line. 
llvm-svn: 117605
 2010-10-28 21:28:01 +00:00
Chris Lattner
9f9f4ebf0c remove the rest of hte owningptr's, no functionality change. 
llvm-svn: 117603
 2010-10-28 20:52:15 +00:00
Chris Lattner
b24ba7be49 rearrange ParseRegisterList. 
llvm-svn: 117560
 2010-10-28 17:23:41 +00:00
Chris Lattner
bd7c9fa36b refactor some code to simplify it, eliminating some owningptr's. 
llvm-svn: 117559
 2010-10-28 17:20:03 +00:00
Chandler Carruth
1898262a33 Remove remaining uses of ATTRIBUTE_UNUSED on variables, and delete three 
#includes in the process.

llvm-svn: 116919
 2010-10-20 08:27:02 +00:00
Chris Lattner
a63292a3ca implement rdar://8456378 and PR7557 - support for the fstsw, 
an instruction that requires a WHOLE NEW wonderful kind of alias.

llvm-svn: 115015
 2010-09-29 01:50:45 +00:00
Chris Lattner
b44fd24fc1 change the protocol TargetAsmPArser::MatchInstruction method to take an 
MCStreamer to emit into instead of an MCInst to fill in.  This allows the
matcher extra flexibility and is more convenient.

llvm-svn: 115014
 2010-09-29 01:42:58 +00:00
Chris Lattner
a2a9d16b78 fix the asmparser so that the target is responsible for skipping to 
the end of the line on a parser error, allowing skipping to happen
for syntactic errors but not for semantic errors.  Before we would
miss emitting a diagnostic about the second line, because we skipped
it due to the semantic error on the first line:

  foo %eax
  bar %al

This fixes rdar://8414033 - llvm-mc ignores lines after an invalid instruction mnemonic errors

llvm-svn: 113688
 2010-09-11 16:18:25 +00:00
Chris Lattner
91689c1d0f change the MC "ParseInstruction" interface to make it the 
implementation's job to check for and lex the EndOfStatement
marker.

llvm-svn: 113347
 2010-09-08 05:10:46 +00:00
Chris Lattner
339cc7bfef in the case where an instruction only has one implementation 
of a mneumonic, report operand errors with better location
info.  For example, we now report:

t.s:6:14: error: invalid operand for instruction
        cwtl $1
             ^

but we fail for common cases like:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^

because we don't know if this is supposed to be the reg/imm or imm/reg
form.

llvm-svn: 113178
 2010-09-06 22:11:18 +00:00
Chris Lattner
a22a368e7c change MatchInstructionImpl to return an enum instead of bool. 
llvm-svn: 113165
 2010-09-06 19:22:17 +00:00
Chris Lattner
3e4582ada5 have AsmMatcherEmitter.cpp produce the hunk of code that gets included 
into the middle of the class, and rework how the different sections of
the generated file are conditionally included for simplicity.

llvm-svn: 113163
 2010-09-06 19:11:01 +00:00
Chris Lattner
94f834348f zap dead code. 
llvm-svn: 112712
 2010-09-01 16:04:34 +00:00