Commit Graph

463 Commits

Author SHA1 Message Date
Alexey Merzlyakov
660e34fd38 [lldb][RISCV] Support optionally disabled FPR for riscv64 (#104547)
The PR adds the support optionally enabled/disabled FP-registers to LLDB
`RegisterInfoPOSIX_riscv64`. This situation might take place for RISC-V
builds having no FP-registers, like RV64IMAC or RV64IMACV.

To aim this, patch adds `opt_regsets` flags mechanism. It re-works
RegisterInfo class to work with flexibly allocated (depending on
`opt_regsets` flag) `m_register_sets` and `m_register_infos` vectors
instead of statically defined structures. The registration of regsets is
being arranged by `m_per_regset_regnum_range` map.

The patch flows are spread to `NativeRegisterContextLinux_riscv64` and
`RegisterContextCorePOSIX_riscv64` classes, that were tested on:
 - x86_64 host working with coredumps
- RV64GC and RV64IMAC targets working with coredumps and natively in
run-time with binaries

`EmulateInstructionRISCV` is out of scope of this patch, and its
behavior did not change, using maximum set of registers.

According testcase built for RV64IMAC (no-FPR) was added to
`TestLinuxCore.py`.
2024-09-04 15:31:59 +01:00
David Spickett
078cb7a4a0 [lldb][RISC-V] Remove unused variable
Added in a1ffabc403.
2024-07-16 09:46:40 +00:00
ita-sc
a1ffabc403 [lldb][riscv] Fix setting breakpoint for undecoded instruction (#90075)
This patch adds an interface GetLastInstrSize to get information about
the size of last tried to be decoded instruction and uses it to set
software breakpoint if the memory can be decoded as instruction.

RISC-V architecture instruction format specifies the length of
instruction in first bits, so we can set a breakpoint for these cases.
This is needed as RISCV have a lot of extensions, that are not supported
by `EmulateInstructionRISCV`.
2024-07-16 10:03:42 +01:00
Pavel Labath
bbd54e08b0 Reapply "[lldb/aarch64] Fix unwinding when signal interrupts a leaf f… (#92503)
…unction (#91321)"

This reapplies fd1bd53ba5, which was
reverted due to a test failure on aarch64/windows. The failure was
caused by a combination of several factors:
- clang targeting aarch64-windows (unlike msvc, and unlike clang
targeting other aarch64 platforms) defaults to -fomit-frame-pointers
- lldb's code for looking up register values for `<same>` unwind rules
is recursive
- the test binary creates a very long chain of fp-less function frames
(it manages to fit about 22k frames before it blows its stack)

Together, these things have caused lldb to recreate the same deep
recursion when unwinding through this, and blow its own stack as well.
Since lldb frames are larger, about 4k frames like this was sufficient
to trigger the stack overflow.

This version of the patch works around this problem by increasing the
frame size of the test binary, thereby causing it to blow its stack
sooner. This doesn't fix the issue -- the same problem can occur with a
real binary -- but it's not very likely, as it requires an infinite
recursion in a simple (so it doesn't use the frame pointer) function
with a very small frame (so you can fit a lot of them on the stack).

A more principled fix would be to make lldb's lookup code non-recursive,
but I believe that's out of scope for this patch.

The original patch description follows:

A leaf function may not store the link register to stack, but we it can
still end up being a non-zero frame if it gets interrupted by a signal.
Currently, we were unable to unwind past this function because we could
not read the link register value.

To make this work, this patch:
- changes the function-entry unwind plan to include the `fp|lr = <same>`
rules. This in turn necessitated an adjustment in the generic
instruction emulation logic to ensure that `lr=[sp-X]` can override the
`<same>` rule.
- allows the `<same>` rule for pc and lr in all
`m_all_registers_available` frames (and not just frame zero).

The test verifies that we can unwind in a situation like this, and that
the backtrace matches the one we computed before getting a signal.
2024-05-21 10:56:26 +02:00
Muhammad Omair Javaid
4b44502ac8 Revert "[lldb/aarch64] Fix unwinding when signal interrupts a leaf function (#91321)"
This reverts commit fd1bd53ba5.

TestInterruptBacktrace was broken on AArch64/Windows as a result of this change.
See lldb-aarch64-windows buildbot here:
https://lab.llvm.org/buildbot/#/builders/219/builds/11261
2024-05-13 16:05:02 +05:00
Pavel Labath
fd1bd53ba5 [lldb/aarch64] Fix unwinding when signal interrupts a leaf function (#91321)
A leaf function may not store the link register to stack, but we it can
still end up being a non-zero frame if it gets interrupted by a signal.
Currently, we were unable to unwind past this function because we could
not read the link register value.

To make this work, this patch:
- changes the function-entry unwind plan to include the `fp|lr = <same>`
rules. This in turn necessitated an adjustment in the generic
instruction emulation logic to ensure that `lr=[sp-X]` can override the
`<same>` rule.
- allows the `<same>` rule for pc and lr in all
`m_all_registers_available` frames (and not just frame zero).

The test verifies that we can unwind in a situation like this, and that
the backtrace matches the one we computed before getting a signal.
2024-05-09 08:47:12 +02:00
Jonas Devlieghere
1b26c25f7e [llvm] Upstream the BridgeOS triple enum value (NFC)
This upstreams the BridgeOS target triple enum value.
2024-02-19 12:20:23 -08:00
Jonas Devlieghere
3b6a8f823b [lldb] Upstream xros support in lldb (#78389)
Upstream support for debugging xros applications through LLDB.
2024-01-17 09:47:08 -08:00
Alex Langford
1e7101a3d9 [lldb][NFCI] TestEmulation should take a Stream ref
`Instruction::TestEmulation` takes a `Stream *` and checks it for validity.
However, this is unnecessary as we can always ensure that we never pass
`nullptr` for the `Stream` argument. The only use of
`Instruction::TestEmulation` currently is `SBInstruction::TestEmulation`
which gets the `Stream` from an `SBStream`, and `SBStream::ref` can
return a `Stream &` guaranteed.

Differential Revision: https://reviews.llvm.org/D154757
2023-07-10 11:17:25 -07:00
David Spickett
956f5c5f6d [lldb] Use SmallVector for handling register data
Previously lldb was using arrays of size kMaxRegisterByteSize to handle
registers. This was set to 256 because the largest possible register
we support is Arm's scalable vectors (SVE) which can be up to 256 bytes long.

This means for most operations aside from SVE, we're wasting 192 bytes
of it. Which is ok given that we don't have to pay the cost of a heap
alocation and 256 bytes isn't all that much overall.

With the introduction of the Arm Scalable Matrix extension there is a new
array storage register, ZA. This register is essentially a square made up of
SVE vectors. Therefore ZA could be up to 64kb in size.

https://developer.arm.com/documentation/ddi0616/latest/

"The Effective Streaming SVE vector length, SVL, is a power of two in the range 128 to 2048 bits inclusive."

"The ZA storage is architectural register state consisting of a two-dimensional ZA array of [SVLB × SVLB] bytes."

99% of operations will never touch ZA and making every stack frame 64kb+ just
for that slim chance is a bad idea.

Instead I'm switching register handling to use SmallVector with a stack allocation
size of kTypicalRegisterByteSize. kMaxRegisterByteSize will be used in places
where we can't predict the size of register we're reading (in the GDB remote client).

The result is that the 99% of small register operations can use the stack
as before and the actual ZA operations will move to the heap as needed.

I tested this by first working out -wframe-larger-than values for all the
libraries using the arrays previously. With this change I was able to increase
kMaxRegisterByteSize to 256*256 without hitting those limits. With the
exception of the GDB server which needs to use a max size buffer.

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D153626
2023-06-27 09:15:12 +00:00
Fangrui Song
65ceb42d63 Replace deprecated startswith_insensitive with starts_with_insensitive 2023-06-05 11:01:27 -07:00
Jonas Devlieghere
3ebb33632a [lldb] Complete OptionValue cleanup (NFC)
Make the `Get.*Value` and `Set.*Value` function private and migrate the
last remaining call sites to the new overloaded/templated functions.
2023-05-14 20:18:47 -07:00
Jonas Devlieghere
fdbe7c7faa [lldb] Refactor OptionValue to return a std::optional (NFC)
Refactor OptionValue to return a std::optional instead of taking a fail
value. This allows the caller to handle situations where there's no
value, instead of being unable to distinguish between the absence of a
value and the value happening the match the fail value. When a fail
value is required, std::optional::value_or() provides the same
functionality.
2023-05-01 21:08:23 -07:00
Alex Langford
e53e1de57e [lldb] Change ObjectValueDictionary to use a StringMap
llvm has a structure for maps where the key's type is a string. Using
that also means that the keys for OptionValueDictionary don't stick
around forever in ConstString's StringPool (even after they are gone).

The only thing we lose here is ordering: iterating over the map where the keys
are ConstStrings guarantees that we iterate in alphabetical order.
StringMap makes no guarantees about the ordering when you iterate over
the entire map.

Differential Revision: https://reviews.llvm.org/D149482
2023-05-01 16:17:24 -07:00
David Spickett
57c8fee1b9 [lldb] Add dummy field to RegisterInfo for register flags use later
This structure is supposed to be trivial, so we cannot simply do
"= nullptr;" on the new member. Doing that means you are non trivial,
regardless of whether you emulate the previously implied constructor somehow.

The next option is to update every use of brace initialisation.

Given that this is some hundreds of lines, this change just adds a dummy
pointer that is set to nullptr. Subsequent changes will actually use that
to point to register flags information.

Note: This change is not clang-format-ted because it changes a bunch of
areas that are not themselves formatted. It would just add noise.

Reviewed By: jasonmolenda, JDevlieghere

Differential Revision: https://reviews.llvm.org/D145568
2023-04-13 11:30:00 +00:00
Martin Storsjö
a8483b9b30 [lldb] Fix a log format warning on Windows, don't assume uint64_t is a long type
On Windows, long is 32 bit, and uint64_t is long long.

Differential Revision: https://reviews.llvm.org/D144078
2023-02-15 14:44:17 +02:00
Kazu Hirata
f6b8f05bb3 Use llvm::byteswap instead of ByteSwap_{16,32,64} (NFC) 2023-01-28 15:22:37 -08:00
Kazu Hirata
55e2cd1609 Use llvm::count{lr}_{zero,one} (NFC) 2023-01-28 12:41:20 -08:00
Hui Li
b7ae5762a1 [LLDB][LoongArch] Add FP branch instructions for EmulateInstructionLoongArch
Add floating-point branch Instructions for EmulateInstructionLoongArch and
add relevant unit tests.

Without this patch:

```
$ ninja check-lldb-unit
[0/1] Running lldb unit test suite

Testing Time: 10.45s
  Passed: 1044
```

With this patch:

```
$ ninja check-lldb-unit
[0/1] Running lldb unit test suite

Testing Time: 10.20s
  Passed: 1048

```

Reviewed By: SixWeining, MaskRay, DavidSpickett

Differential Revision: https://reviews.llvm.org/D140759
2023-01-14 09:22:18 +08:00
Emmmer
0ef58c66c6 [LLDB][RISCV] Add RVDC instruction support for EmulateInstructionRISCV
RVC is the RISC-V standard compressed instruction-set extension, named "C", which reduces static and dynamic code size by adding short 16-bit instruction encodings for common operations, and RVCD is the compressed "D extension".

And "D extension" is a double-precision floating-point instruction-set extension, which adds double-precision floating-point computational instructions compliant with the IEEE 754-2008 arithmetic standard.

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D140961
2023-01-13 20:52:34 +08:00
Hui Li
1eaadaea50 [LLDB][LoongArch] Add unittests for EmulateInstructionLoongArch
Add unit tests For EmulateInstructionLoongArch existing branch instruction.
Add 19 test cases in total.

Without this patch:

```
$ ninja check-lldb-unit
[0/1] Running lldb unit test suite

Testing Time: 10.55s
  Passed: 1025
```

With this patch:

```
$ ninja check-lldb-unit
[0/1] Running lldb unit test suite

Testing Time: 10.45s
  Passed: 1044
```

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D140386
2023-01-13 10:17:55 +08:00
Kazu Hirata
570117b6a5 [lldb] Remove remaining uses of llvm::Optional (NFC)
This patch removes the unused "using" declarations, updates comments,
and removes #include "llvm/ADT/Optional.h".

This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2023-01-07 14:36:35 -08:00
Kazu Hirata
2fe8327406 [lldb] Use std::optional instead of llvm::Optional (NFC)
This patch replaces (llvm::|)Optional< with std::optional<.  I'll post
a separate patch to clean up the "using" declarations, #include
"llvm/ADT/Optional.h", etc.

This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2023-01-07 14:18:35 -08:00
Kazu Hirata
f190ce625a [lldb] Add #include <optional> (NFC)
This patch adds #include <optional> to those files containing
llvm::Optional<...> or Optional<...>.

I'll post a separate patch to actually replace llvm::Optional with
std::optional.

This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2023-01-07 13:43:00 -08:00
Hui Li
3473c1093a [LLDB][LoongArch] Optimize EmulateInstructionLoongArch related code
This is a code optimization patch that does not include feature additions
or deletions.

Reviewed By: SixWeining

Differential Revision: https://reviews.llvm.org/D140616
2022-12-28 09:13:05 +08:00
Kazu Hirata
81d1b61e90 [lldb] Fix a warning
This patch fixes:

  lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp:1378:16:
  warning: control reaches end of non-void function [-Wreturn-type]
2022-12-22 12:01:35 -08:00
Fangrui Song
f43886e7ba [lldb] llvm::Optional::value() && => operator*/operator->
std::optional::value() has undesired exception checking semantics and is
unavailable in older Xcode (see _LIBCPP_AVAILABILITY_BAD_OPTIONAL_ACCESS). The
call sites block std::optional migration.
2022-12-17 20:37:13 +00:00
Fangrui Song
9464bd8c78 [lldb] llvm::Optional::value => operator*/operator->
std::optional::value() has undesired exception checking semantics and is
unavailable in some older Xcode. The call sites block std::optional migration.
2022-12-17 05:01:54 +00:00
Hui Li
eafe2d4cf1 [LLDB][LoongArch] Add branch instructions for EmulateInstructionLoongArch
Add conditional and unconditional branch instructions for loongarch64.
Note that this does not include floating-point branch instructions, that will come in a later patch.

Reviewed By: SixWeining, DavidSpickett

Differential Revision: https://reviews.llvm.org/D139833
2022-12-16 17:48:37 +08:00
Emmmer
d850b340a9 Fix: use "using namespace" in a header file. 2022-12-16 03:31:10 +08:00
Emmmer
5aed2eff43 Fix buildbot out of memory
https://lab.llvm.org/buildbot#builders/17/builds/31659
2022-12-16 02:20:19 +08:00
Kazu Hirata
c12c90d8f5 [lldb] Fix a warning
This patch fixes:

  lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp:1402:18:
  error: default label in switch which covers all enumeration values
  [-Werror,-Wcovered-switch-default]
2022-12-15 09:18:55 -08:00
Emmmer
6493fc4bcc [LLDB][RISCV] Add RVD instruction support for EmulateInstructionRISCV
RVD extension is a double-precision floating-point instruction-set extension, which adds double-precision floating-point computational instructions compliant with the IEEE 754-2008 arithmetic standard.

This patch:
- Reuse most of the functions in the "F extension" to impl the"D extension"
- corresponding unittests.

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D140032
2022-12-16 00:58:26 +08:00
Emmmer
260ba2f224 [NFC][LLDB] Using namespace llvm in EmulateInstructionRISCV
The `EmulateInstructionRISCV` uses a lot of types and functions in `llvm` and `lldb`, this change is to make the code look cleaner.

PS: This patch should be merged before D140032.

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D140092
2022-12-15 21:32:20 +08:00
Kazu Hirata
230df792e1 [lldb] Use llvm::transformOptional (NFC)
This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-14 18:36:49 -08:00
Kazu Hirata
8b5c302efb [lldb] Use std::optional instead of None in comments (NFC)
This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-10 17:06:43 -08:00
Hui Li
f0f33957d0 [LLDB][LoongArch] Make software single stepping work
Hardware single stepping is not currently supported by the linux kernel.
In order to support single step debugging, add EmulateInstructionLoongArch
to implement the software Single Stepping. This patch only support the
simplest single step execution of non-jump instructions.

Reviewed By: SixWeining, DavidSpickett

Differential Revision: https://reviews.llvm.org/D139158
2022-12-08 19:59:39 +08:00
Weining Lu
2bfef8d537 Revert "[LLDB][LoongArch] Make software single stepping work"
This reverts commit 3a9e07b1e7.

Reason to revert: author name is wrong.
2022-12-08 19:56:58 +08:00
Weining Lu
3a9e07b1e7 [LLDB][LoongArch] Make software single stepping work
Hardware single stepping is not currently supported by the linux kernel.
In order to support single step debugging, add EmulateInstructionLoongArch
to implement the software Single Stepping. This patch only support the
simplest single step execution of non-jump instructions.

Reviewed By: SixWeining, DavidSpickett

Differential Revision: https://reviews.llvm.org/D139158
2022-12-08 19:06:07 +08:00
Emmmer
d3628823c9 [LLDB][RISCV] Add RV32FC instruction support for EmulateInstructionRISCV
Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D139390
2022-12-06 22:26:51 +08:00
Emmmer
2d7f43f9ea [LLDB][RISCV] Add RV64F instruction support for EmulateInstructionRISCV
Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D139294
2022-12-05 22:54:08 +08:00
Fangrui Song
a996cc217c Remove unused #include "llvm/ADT/Optional.h" 2022-12-05 06:31:11 +00:00
Fangrui Song
3dfacc0a56 CheckedArithmetic: llvm::Optional => std::optional 2022-12-05 04:30:54 +00:00
Kazu Hirata
768cae4a5a [lldb] Use std::nullopt instead of None in comments (NFC)
This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-04 20:11:39 -08:00
Kazu Hirata
343523d040 [lldb] Use std::nullopt instead of None (NFC)
This patch mechanically replaces None with std::nullopt where the
compiler would warn if None were deprecated.  The intent is to reduce
the amount of manual work required in migrating from Optional to
std::optional.

This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-04 16:51:25 -08:00
Jordan Rupprecht
cd02e78cd5 [NFC] Make headers self-contained.
Some headers in LLDB work only when considered as textual inclusion, but not if one attempts to use them on their own or with a different context.

- python-typemaps.h: uses Python definitions without using "Python.h".
- RISCVCInstructions.h uses RISC-V register enums without including the enums header.
- RISCVInstructions.h includes EmulateInstructionRISCV.h, but is unnecessary since we forward-declare EmulateInstructionRISCV anyway. Including the header is problematic because EmulateInstructionRISCV.h uses DecodeResult which isn't defined until later in RISCVInstructions.h.

This makes LLDB build cleanly with the "parse_headers" feature [1]. I'm not sure what the analagous CMake option is.

[1] I didn't find public documentation but @MaskRay wrote this up: https://maskray.me/blog/2022-09-25-layering-check-with-clang#parse_headers

Reviewed By: labath, MaskRay

Differential Revision: https://reviews.llvm.org/D138310
2022-11-29 04:14:55 -08:00
Kazu Hirata
a2f1879c2d [lldb] Fix a warning
This patch fixes:

  lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp:105:18:
  warning: comparison of unsigned expression in ‘>= 0’ is always true
  [-Wtype-limits]
2022-11-23 15:55:05 -08:00
Emmmer
6d4ab6d921 [LLDB][RISCV] Add RV32F instruction support for EmulateInstructionRISCV
Add:

- RV32F instruction set.
- corresponding unittests.

Further work:

- RV32FC, RV64F and RV64FC instructions support.
- update execution exceptions to fcsr register in RVM instructions.

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D138447
2022-11-23 22:09:14 +08:00
Benjamin Kramer
b6cf94e973 Fix format specifier warning in EmulateInstructionRISCV more
Yes, the portable macro is still the only way to do this.
2022-11-04 18:58:43 +01:00
Jonas Devlieghere
234e08ec3c [lldb] Fix format specifier warning in EmulateInstructionRISCV
Fixes warning: format specifies type 'unsigned long' but the argument
has type 'lldb::addr_t' (aka 'unsigned long long') [-Wformat]
2022-11-04 10:46:31 -07:00