Commit Graph

454 Commits

Author SHA1 Message Date
Abid Qadeer
89f2d50cda [mlir][debug] Support DIGenericSubrange. (#113441)
`DIGenericSubrange` is used when the dimensions of the arrays are
unknown at build time (e.g. assumed-rank arrays in Fortran). It has same
`lowerBound`, `upperBound`, `count` and `stride` fields as in
`DISubrange` and its translation looks quite similar as a result.

---------

Co-authored-by: Tobias Gysi <tobias.gysi@nextsilicon.com>
2024-10-31 10:09:26 +00:00
Sirui Mu
1dfb104eac [mlir][LLVMIR] Add operand bundle support for llvm.intr.assume (#112143)
This patch adds operand bundle support for `llvm.intr.assume`.

This patch actually contains two parts:

- `llvm.intr.assume` now accepts operand bundle related attributes and
operands. `llvm.intr.assume` does not take constraint on the operand
bundles, but obviously only a few set of operand bundles are meaningful.
I plan to add some of those (e.g. `aligned` and `separate_storage` are
what interest me but other people may be interested in other operand
bundles as well) in future patches.

- The definitions of `llvm.call`, `llvm.invoke`, and
`llvm.call_intrinsic` actually define `op_bundle_tags` as an operation
property. It turns out this approach would introduce some unnecessary
burden if applied equally to the intrinsic operations because properties
are not available through `Operation *` but we have to operate on
`Operation *` during the import/export of intrinsics, so this PR changes
it from a property to an array attribute.

This patch relands commit d8fadad07c.
2024-10-16 20:49:02 +08:00
Sirui Mu
484c02780b Revert "[mlir][LLVMIR] Add operand bundle support for llvm.intr.assume (#112143)"
This reverts commit d8fadad07c.

The commit breaks the following CI builds:
- ppc64le-mlir-rhel-clang: https://lab.llvm.org/buildbot/#/builders/129/builds/7685
- ppc64le-flang-rhel-clang: https://lab.llvm.org/buildbot/#/builders/157/builds/10338
2024-10-16 14:15:31 +08:00
Sirui Mu
d8fadad07c [mlir][LLVMIR] Add operand bundle support for llvm.intr.assume (#112143)
This patch adds operand bundle support for `llvm.intr.assume`.

This patch actually contains two parts:

- `llvm.intr.assume` now accepts operand bundle related attributes and
operands. `llvm.intr.assume` does not take constraint on the operand
bundles, but obviously only a few set of operand bundles are meaningful.
I plan to add some of those (e.g. `aligned` and `separate_storage` are
what interest me but other people may be interested in other operand
bundles as well) in future patches.

- The definitions of `llvm.call`, `llvm.invoke`, and
`llvm.call_intrinsic` actually define `op_bundle_tags` as an operation
property. It turns out this approach would introduce some unnecessary
burden if applied equally to the intrinsic operations because properties
are not available through `Operation *` but we have to operate on
`Operation *` during the import/export of intrinsics, so this PR changes
it from a property to an array attribute.
2024-10-16 12:51:50 +08:00
ravil-mobile
d741435d77 [MLIR][ROCDL] Added SchedGroupBarrier and IglpOpt ops (#112237)
This PR adds missing `sched.group.barrier` and `rocdl.iglp.opt` ops to
the ROCDL dialect (see
[here](ec78f0da0e/clang/include/clang/Basic/BuiltinsAMDGPU.def (L66-L68))).
The ops are converted to the corresponding intrinsic calls during the
translation from MLIR to LLVM IRs. This intrinsics are hints to the
instruction scheduler of the AMDGPU backend.
2024-10-15 22:54:39 +01:00
Sergio Afonso
0a17bdfc36 [MLIR][OpenMP] Remove terminators from loop wrappers (#112229)
This patch simplifies the representation of OpenMP loop wrapper
operations by introducing the `NoTerminator` trait and updating
accordingly the verifier for the `LoopWrapperInterface`.

Since loop wrappers are already limited to having exactly one region
containing exactly one block, and this block can only hold a single
`omp.loop_nest` or loop wrapper and an `omp.terminator` that does not
return any values, it makes sense to simplify the representation of loop
wrappers by removing the terminator.

There is an extensive list of Lit tests that needed updating to remove
the `omp.terminator`s adding some noise to this patch, but actual
changes are limited to the definition of the `omp.wsloop`, `omp.simd`,
`omp.distribute` and `omp.taskloop` loop wrapper ops, Flang lowering for
those, `LoopWrapperInterface::verifyImpl()`, SCF to OpenMP conversion
and OpenMP dialect documentation.
2024-10-15 11:28:39 +01:00
Abid Qadeer
cd12ffb622 [mlir][debug] Allow multiple DIGlobalVariableExpression on globals. (#111981)
Currently, we allow only one DIGlobalVariableExpressionAttr per global.
It is especially evident in import where we pick the first from the list
and ignore the rest. In contrast, LLVM allows multiple
DIGlobalVariableExpression to be attached to the global. They are needed
for correct working of things like DICommonBlock. This PR removes this
restriction in mlir. Changes are mostly mechanical. One thing on which I
went a bit back and forth was the representation inside GlobalOp. I
would be happy to change if there are better ways to do this.

---------

Co-authored-by: Tobias Gysi <tobias.gysi@nextsilicon.com>
2024-10-13 23:36:00 +01:00
Abid Qadeer
36c34ec967 [mlir][debug] Support DICommonBlock. (#111706)
A COMMON block is a named area of memory that holds a collection of
variables. Fortran subprograms may map the COMMON block memory area to a
list of variables. A common block is represented in LLVM debug by
DICommonBlock.

This PR adds support for this in MLIR. The changes are mostly mechanical
apart from small change to access the DICompileUnit when the scope of
the variable is DICommonBlock.

---------

Co-authored-by: Tobias Gysi <tobias.gysi@nextsilicon.com>
2024-10-10 18:07:06 +01:00
Walter Erquinigo
2918e779a9 [mlir][debuginfo] Add support for subprogram annotations (#110946)
LLVM already supports `DW_TAG_LLVM_annotation` entries for subprograms,
but this hasn't been surfaced to the LLVM dialect.
I'm doing the minimal amount of work to support string-based
annotations, which is useful for attaching metadata to
functions, which is useful for debuggers to offer features beyond basic
DWARF.
As LLVM already supports this, this patch is not controversial.
2024-10-07 17:51:08 -04:00
Ilya V
1b4b0c4c45 Allow fixed vector operand for LLVM_AtomicRMWOp (#110553)
This PR fixes `LLVM_AtomicRMWOp` allowed semantics and verifier logic to
enable building of `LLVM_AtomicRMWOp` with fixed vectors of compatible
fp values
as operands for fp rmw operation.

See also: https://llvm.org/docs/LangRef.html#id231

Signed-off-by: Ilya Veselov <iveselov.nn@gmail.com>
2024-10-03 18:15:29 +01:00
Sirui Mu
fde3c16ac9 [mlir][LLVM] Add operand bundle support (#108933)
This PR adds LLVM [operand
bundle](https://llvm.org/docs/LangRef.html#operand-bundles) support to
MLIR LLVM dialect. It affects these 3 operations related to making
function calls: `llvm.call`, `llvm.invoke`, and `llvm.call_intrinsic`.

This PR adds two new parameters to each of the 3 operations. The first
parameter is a variadic operand `op_bundle_operands` that contains the
SSA values for operand bundles. The second parameter is a property
`op_bundle_tags` which holds an array of strings that represent the tags
of each operand bundle.
2024-09-26 07:59:37 +02:00
Daniel Hernandez-Juarez
b014265d99 [mlir][AMDGPU] New gfx12 barrier instructions and update lowering LDSBarrierOp (#109273)
New gfx12 barrier instructions: s.barrier.signal, s.barrier.wait and
s.wait.dscnt. And update lowering LDSBarrierOp accordingly.

CC: @krzysz00 @manupak @giuseros
2024-09-20 17:41:36 -05:00
Chuanqi Xu
e8a7390624 [mlir] [LLVM IR] Introduce VaArgOp (#109260)
I find there is no LLVMOp corresponding to LLVM's [va_arg
instruction](https://llvm.org/docs/LangRef.html#va-arg-instruction) so I
tried to add one. This is helpful for clangir
(https://github.com/llvm/clangir/pull/865).

New to MLIR and not sure who are the appropriate reviewers. Appreciated
in ahead for reviewing and triaging.
2024-09-20 13:19:50 +08:00
Jianjian Guan
87dc3e89e7 [mlir][LLVMIR] Add more vector predication intrinsic ops (#107663)
This revision adds vector predication smax, smin, umax and umin
intrinsic ops.
2024-09-19 10:33:36 +08:00
Rajveer Singh Bharadwaj
1c4b04ce1f [mlir] Fix crash in InsertOpConstantFolder when vector.insert operand is from a llvm.mlir.constant op (#88314)
In cases where llvm.mlir.constant has an attribute with a different type than the returned type,
the folder use to create an incorrect DenseElementsAttr and crash.

Resolves #74236
2024-09-09 01:44:30 +02:00
Observer007
097138f0ce [mlir] Add option to control the emissionKind to DIScopeForLLVMFuncOp pass (#106229)
This is currently not controllable by the user and always set to
`DIEmissionKind::LineTablesOnly`.
The added option allows to set it to the other values accepted by LLVM
(`None`, `Full`, and `DebugDirectivesOnly`).

---------

Co-authored-by: jingzec <jingzec@nvidia.com>
2024-08-28 13:31:47 +08:00
Sirui Mu
318b0678e3 [mlir][LLVM] Add support for constant struct with multiple fields (#102752)
Currently `mlir.llvm.constant` of structure types restricts that the
structure type effectively represents a complex type -- it must have
exactly two fields of the same type and the field type must be either an
integer type or a float type.

This PR relaxes this restriction and it allows the structure type to
have an arbitrary number of fields.
2024-08-22 15:32:55 +02:00
Christian Ulmann
bf68e9047f [MLIR] Introduce a SelectLikeOpInterface (#104751)
This commit introduces a `SelectLikeOpInterface` that can be used to
handle select-like operations generically. Select operations are similar
to control flow operations, as they forward operands depending on
conditions. This is the reason why it was placed to the already existing
control flow interfaces.
2024-08-20 07:32:12 +02:00
Christian Ulmann
065d2d9c60 [MLIR][LLVM] Improve the noalias propagation during inlining (#104750)
This commit changes the LLVM dialect's inliner interface to properly
propagate noalias information to memory accesses that have different
underlying object. By always introducing an SSACopy intrinsic, it's
possible to understand that specific memory operations are using
unrelated pointers. Previously, the backwards slice walk did continue
beyond the boundary of the original function and failed to reason about
the "underlying objects".
2024-08-19 11:27:30 +02:00
Christian Ulmann
141536544f [MLIR][LLVM]: Add an IR utility to perform slice walking (#103053)
This commit introduces a slicing utility that can be used to walk
arbitrary IR slices. It additionally ships logic to determine control
flow predecessors, which allows users to walk backward slices without
dealing with both `RegionBranchOpInterface` and `BranchOpInterface`.

This utility is used to improve the `noalias` propagation in the LLVM
dialect's inliner interface. Before this change, it broke down as soon
as pointer were passed through region control flow operations.
2024-08-15 10:30:44 +02:00
Matthias Springer
b8bf14eecf [mlir][LLVMIR] Check number of elements in mlir.constant verifier (#102906)
Check that the number of elements in the result type and the attribute
of an `llvm.mlir.constant` op matches. Also fix a broken test where that
was not the case.
2024-08-13 10:39:49 +02:00
Victor Perez
d45de8003a [MLIR][GPU-LLVM] Convert gpu.func to llvm.func (#101664)
Add support in `-convert-gpu-to-llvm-spv` to convert `gpu.func` to
`llvm.func` operations.

- `spir_kernel`/`spir_func` calling conventions used for
kernels/functions.
- `workgroup` attributions encoded as additional `llvm.ptr<3>`
arguments.
- No attribute used to annotate kernels
- `reqd_work_group_size` attribute using to encode
`gpu.known_block_size`.
- `llvm.mlir.workgroup_attrib_size` used to encode workgroup attribution
sizes. This will be attached to the pointer argument workgroup
attributions lower to.

**Note**: A notable missing feature that will be addressed in a
follow-up PR is a `-use-bare-ptr-memref-call-conv` option to replace
MemRef arguments with bare pointers to the MemRef element types instead
of the current MemRef descriptor approach.

---------

Signed-off-by: Victor Perez <victor.perez@codeplay.com>
2024-08-09 16:09:11 +02:00
Andrzej Warzyński
673604a539 [mlir][vector] Update docs for scalable vectors (#101842)
Adds a few notes on scalable vectors in the docs for the Vector dialect.
This is mostly "repeating" things from LLVM's LangRef. 

Additionally:

* Adds a few basic tests with scalable vectors (those should've been
  added long time ago),
* Updates a comment in "TypeConverter.cpp" (the current comment is
out-of-date),
* Includes small formatting edits in Vector.md.

**NOTE** Depends on #101813 - only review the top commit
2024-08-06 11:52:55 +01:00
Victor Perez
6d2bbba187 [MLIR][LLVM] Attach kernel metadata representation to llvm.func (#101314)
Add optional attributes to `llvm.func` representing LLVM so-called
"kernel" metadata:

-
[`vec_type_hint`](https://clang.llvm.org/docs/AttributeReference.html#vec-type-hint)
-
[`work_group_size_hint`](https://clang.llvm.org/docs/AttributeReference.html#work-group-size-hint)
-
[`reqd_work_group_size`](https://clang.llvm.org/docs/AttributeReference.html#reqd-work-group-size)
-
[`intel_reqd_sub_group_size`](https://clang.llvm.org/docs/AttributeReference.html#intel-reqd-sub-group-size).

---------

Signed-off-by: Victor Perez <victor.perez@codeplay.com>
2024-08-02 11:53:30 +02:00
James Y Knight
dfeb3991fb Remove the x86_mmx IR type. (#98505)
It is now translated to `<1 x i64>`, which allows the removal of a bunch
of special casing.

This _incompatibly_ changes the ABI of any LLVM IR function with
`x86_mmx` arguments or returns: instead of passing in mmx registers,
they will now be passed via integer registers. However, the real-world
incompatibility caused by this is expected to be minimal, because Clang
never uses the x86_mmx type -- it lowers `__m64` to either `<1 x i64>`
or `double`, depending on ABI.

This change does _not_ eliminate the SelectionDAG `MVT::x86mmx` type.
That type simply no longer corresponds to an IR type, and is used only
by MMX intrinsics and inline-asm operands.

Because SelectionDAGBuilder only knows how to generate the
operands/results of intrinsics based on the IR type, it thus now
generates the intrinsics with the type MVT::v1i64, instead of
MVT::x86mmx. We need to fix this before the DAG LegalizeTypes, and thus
have the X86 backend fix them up in DAGCombine. (This may be a
short-lived hack, if all the MMX intrinsics can be removed in upcoming
changes.)

Works towards issue #98272.
2024-07-25 09:19:22 -04:00
Finlay
2eea9d6a2d [mlir] Rename memory attribute to memory_effects in llvmir dialect (#100108)
This commit renames the memory attribute on operations to "memory_effects" to be in line with the naming LLVM IR is using.
2024-07-23 14:17:05 +02:00
Finlay
fde27bd221 [mlir] Added new attributes to the llvm.call op in llvmir target (#99663)
The new attributes are:
 * convergent
 * no_unwind
 * will_return
 * memory effects
2024-07-23 12:44:13 +02:00
Tobias Gysi
5da4310082 [MLIR][LLVM] Always print variadic callee type (#99293)
This commit updates the LLVM dialect CallOp and InvokeOp to always print
the variadic callee type (previously callee type) if present. An
additional verifier checks that only variadic calls have a non-null
variadic callee type, and the builders are adapted accordingly to set
the variadic callee type for variadic calls only. Finally, the CallOp
and InvokeOp verifiers are strengthened to check that the variadic
callee type matches the call argument and result types.

The motivation of this change is that CallOp and InvokeOp don't have
hidden state that is not pretty printed, but used during the export to
LLVM IR. Previously, it could happen that a call looked correct in MLIR,
but the return type changed after exporting to LLVM IR (since it has
been taken from the hidden callee type attribute). After landing this
change, this is not possible anymore since the variadic callee type is
always printed if present.
2024-07-23 08:21:46 +02:00
Finlay
aa21ee7926 [MLIR] Add attributes no_unwind and will_return to the LLVMIR dialect (#98921)
And testing.
These are being added to be used in the GPU to LLVM SPV pass.

---------

Co-authored-by: Victor Perez <victor.perez@codeplay.com>
2024-07-17 11:26:25 +02:00
Steffi Stumpos
4a01079931 Expose Tail Kind Call to MLIR (#98080)
I would like to mark a call op in LLVM dialect as Musttail. The calling
convention attribute only exposes Tail, not Musttail. I noticed that the
CallInst of LLVM has an additional field to specify the flavor of tail
call kind. I bubbled this up to the LLVM dialect by adding another
attribute that maps to LLVM::CallInst::TailCallKind.
2024-07-09 14:04:33 -07:00
runseny
e5865ec93c [MLIR][LLVM] Add ftz and fuse FP ops related function attribute support (#97812)
Adds `denormal-fp-math-f32`, `denormal-fp-math`, `fp-contract` to
llvmFuncOp attributes.

`denormal-fp-math-f32` and `denormal-fp-math` can enable the ftz, that
is , flushing denormal to zero.

`fp-contract` can enable the fma fusion such as `mul + add -> fma`
2024-07-09 09:34:43 +01:00
Finlay
d6df01870a [MLIR] Add the convergent attribute to LLVM Dialect (#97709)
In order to use the convergent attribute in the GPUToLLVMSPV pass, I've
added the attribute to the LLVM dialect.
Some details on the convergent attribute
https://llvm.org/docs/ConvergentOperations.html#convergent-operations
2024-07-05 09:33:56 +02:00
Stephen Tozer
094572701d [RemoveDIs] Print IR with debug records by default (#91724)
This patch makes the final major change of the RemoveDIs project, changing the
default IR output from debug intrinsics to debug records. This is expected to
break a large number of tests: every single one that tests for uses or
declarations of debug intrinsics and does not explicitly disable writing
records. 

If this patch has broken your downstream tests (or upstream tests on a
configuration I wasn't able to run):
1. If you need to immediately unblock a build, pass
`--write-experimental-debuginfo=false` to LLVM's option processing for all
failing tests (remember to use `-mllvm` for clang/flang to forward arguments to
LLVM).
2. For most test failures, the changes are trivial and mechanical, enough that
they can be done by script; see the migration guide for a guide on how to do
this: https://llvm.org/docs/RemoveDIsDebugInfo.html#test-updates
3. If any tests fail for reasons other than FileCheck check lines that need
updating, such as assertion failures, that is most likely a real bug with this
patch and should be reported as such.

For more information, see the recent PSA:
https://discourse.llvm.org/t/psa-ir-output-changing-from-debug-intrinsics-to-debug-records/79578
2024-06-14 15:07:27 +01:00
Johannes de Fine Licht
c012e487b7 [MLIR][LLVM] Promote noinline/alwaysinline/optnone out of passthrough (#95110)
The `noinline`, `alwaysinline`, and `optnone` function attributes are
already being used in MLIR code for the LLVM inlining interface and in
some SPIR-V lowering, despite residing in the passthrough dictionary,
which is intended as exactly that -- a pass through MLIR -- and not to
model any actual semantics being handled in MLIR itself.

Promote the `noinline`, `alwaysinline`, and `optnone` attributes out of
the passthrough dictionary on `llvm.func` into first class unit
attributes, updating the import and export accordingly.

Add a verifier to `llvm.func` that checks that these attributes are not
set in an incompatible way according to the LLVM specification.

Update the LLVM dialect inlining interface to use the first class
attributes to check whether inlining is possible.
2024-06-12 08:29:02 +02:00
Christian Ulmann
6168e82c1e [MLIR][LLVM] Add inlining support for loop annotations (#94447)
This commit extends the LLVM dialect's inliner interface support
updating loop annotation attributes. This is necessary because the loop
annotations can contain debug locations, which are verified by LLVM's
verifier. LLVM requires these locations to have the same scope as the
function this attribute is contained in.
2024-06-05 14:08:00 +02:00
Jay Foad
f6c8e7dc3e [MLIR][AMDGPU] Remove support for old llvm.amdgcn.buffer.* intrinsics (#93838)
They have been superseded by llvm.amdgcn.raw.buffer.* and
llvm.amdgcn.struct.buffer.*.
2024-05-30 17:58:11 +01:00
Guy David
4bce270157 [mlir][llvm] Implement ConstantLike for ZeroOp, UndefOp, PoisonOp (#93690)
These act as constants and should be propagated whenever possible. It is
safe to do so for mlir.undef and mlir.poison because they remain "dirty"
through out their lifetime and can be duplicated, merged, etc. per the
LangRef.

Signed-off-by: Guy David <guy.david@nextsilicon.com>
2024-05-30 08:21:08 +02:00
Christian Ulmann
6a3982f8b7 [MLIR][LLVM] Relax the LLVM dialect's inliner assuming UCF (#93514)
This commit changes the LLVM dialect's inliner interface to stop
assuming that the inlined function only contained unstructured control
flow. This is not necessarily true, and it lead to not properly
propagating the noalias information.
2024-05-30 07:58:13 +02:00
Christian Ulmann
2171f34121 [MLIR][LLVM] Remove the type consistency pass (#93283)
This commit removes the LLVM dialect's type consistency pass. This pass
was originally introduced to make type information on memory operations
consistent. The main benefactor of this consistency where Mem2Reg and
SROA, which were in the meantime improved to no longer require
consistent type information.

Apart from providing a no longer required functionality, the pass had
some fundamental flaws that lead to issues:
* It introduced trivial GEPs (only zero indices) that could be folded
again.
* Aggressively splitting stores lead to substantial performance
regressions in some cases. Subsequent memory coalescing were not able to
recover this information, due to using non-trivial bit-fiddling.
2024-05-24 13:22:30 +02:00
klensy
f0b0c02504 [mlir][test] Fix filecheck annotation typos (#92897)
Moved fixes for mlir from
https://github.com/llvm/llvm-project/pull/91854, plus few additional in
second commit.

---------

Co-authored-by: klensy <nightouser@gmail.com>
2024-05-24 09:24:59 +02:00
William G Hatch
5c35b63da3 [MLIR][LLVM] add dwarfAddressSpace to DIDerivedType (#92043)
This field is present in LLVM, but was missing from the MLIR wrapper
type. This addition allows MLIR languages to add proper DWARF info for
GPU programs.
2024-05-16 08:24:56 +02:00
Christian Ulmann
e6216906f5 [MLIR][LLVM] Improve atomic verifier to properly support larger types (#92120)
This commit extends the verifier for atomics to properly verify larger
types. Beforehand, the verifier strictly rejected larger integer types,
while it now consults the data layout to determine if their bitsize is a
power of two. This behavior reflects what LLVM's verifier is checking
for.
2024-05-15 08:31:09 +02:00
Mubashar Ahmad
e1685eb8d7 [mlir][llvm] Add llvm.vector.deinterleave2 intrinsic (#91986)
Adds the LLVM vector.deinterleave2 intrinsic to the MLIR LLVM dialect. The 
deinterleave2 intrinsic takes a vector and returns two vectors with the first 
having even elements and the second with odd elements from the input 
vector. The inverse of vector.interleave2.
2024-05-14 14:32:50 +01:00
Thomas Raoux
5526c8a742 [MLIR] Model llvm.inline_asm side_effects (#91507)
Allow more cleanups on inline_asm ops modeling side effects based on the
side_effect attributed.
2024-05-08 12:35:15 -07:00
Johannes de Fine Licht
92ca6fcb87 [MLIR][LLVM] Have LLVM::AddressOfOp implement ConstantLike (#90481)
For all means and purposes llvm.mlir.addressof acts like a constant, and
should be treated as such by passes. In particular, the operation should
be propagated rather than passed whenever possible.
2024-04-30 10:00:28 +02:00
Maciej Gabka
bfc0317153 Move several vector intrinsics out of experimental namespace (#88748)
This patch is moving out following intrinsics:
* vector.interleave2/deinterleave2
* vector.reverse
* vector.splice

from the experimental namespace.

All these intrinsics exist in LLVM for more than a year now, and are
widely used, so should not be considered as experimental.
2024-04-29 10:16:45 +01:00
Sergio Afonso
07e6c1609d [MLIR][OpenMP] Make omp.wsloop into a loop wrapper (1/5) (#89209)
This patch updates the definition of `omp.wsloop` to enforce the
restrictions of a loop wrapper operation.

Related tests are updated but this PR on its own will not pass premerge
tests. All patches in the stack are needed before it can be compiled and
passes tests.
2024-04-24 14:22:59 +01:00
Christian Ulmann
6e9ea6ea68 [MLIR][LLVM][Mem2Reg] Extends support for partial stores (#89740)
This commit enhances the LLVM dialect's Mem2Reg interfaces to support
partial stores to memory slots. To achieve this support, the `getStored`
interface method has to be extended with a parameter of the reaching
definition, which is now necessary to produce the resulting value after
this store.
2024-04-24 14:28:15 +02:00
Christian Ulmann
ac39fa740b [MLIR][Mem2Reg][LLVM] Enhance partial load support (#89094)
This commit improves LLVM dialect's Mem2Reg interfaces to support
promotions of partial loads from larger memory slots. To support this,
the Mem2Reg interface methods are extended with additional data layout
parameters. The data layout is required to determine type sizes to
produce correct conversion sequences.

Note: There will be additional followups that introduce a similar
functionality for stores, and there are plans to support accesses into
the middle of memory slots.
2024-04-18 13:09:16 +02:00
Christian Ulmann
541962306d [MLIR][LLVM] Remove bitcast pattern from type consistency pass (#87755)
This commit removes the no longer required bitcast inserting pattern in
LLVM dialect's type consistency pattern. This was previously required to
enable Mem2Reg and SROA to promote accesses that had different types.
Recent changes to both passes added direct support for this feature to
them, so the pattern has no further use.
2024-04-05 15:47:16 +02:00