Commit Graph

842 Commits

Author SHA1 Message Date
Jan Vesely
b670d37105 R600: Use SIGN_EXTEND_INREG for SEXT loads
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com>
llvm-svn: 238229
2015-05-26 18:07:22 +00:00
Tom Stellard
ec87f841c6 R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips
The src and dst register cannot be the same on chips with 16 lds banks.

llvm-svn: 238147
2015-05-25 16:15:54 +00:00
Matt Arsenault
65ad1602b0 Add target hook to allow merging stores of nonzero constants
On GPU targets, materializing constants is cheap and stores are
expensive, so only doing this for zero vectors was silly.

Most of the new testcases aren't optimally merged, and are for
later improvements.

llvm-svn: 238108
2015-05-24 00:51:27 +00:00
Tom Stellard
28d13a4b12 R600/SI: add pass to mark CF live ranges as non-spillable
Spilling can insert instructions almost anywhere, and this can mess
up control flow lowering in a multitude of ways, due to instruction
reordering. Let's sort this out the easy way: never spill registers
involved with control flow, i.e. saved EXEC masks.

Unfortunately, this does not work at all with optimizations disabled,
as the register allocator ignores spill weights. This should be
addressed in a future commit.

The test was reduced from the "stacks" shader of [1]. Some issues
trigger the machine verifier while another one is checked manually.

[1] http://madebyevan.com/webgl-path-tracing/

v2: only insert pass with optimizations enabled, merge test runs.

Patch by: Grigori Goronzy

llvm-svn: 237152
2015-05-12 17:13:02 +00:00
Tom Stellard
8f96dfc9ea R600/SI: Remove M0Reg register class
It is no longer used.

llvm-svn: 237142
2015-05-12 15:00:52 +00:00
Tom Stellard
381a94a764 R600/SI: Remove explicit m0 operand from DS instructions
Instead add m0 as an implicit operand.  This helps avoid spills
of the m0 register in some cases.

llvm-svn: 237141
2015-05-12 15:00:49 +00:00
Tom Stellard
7b222e110f R600/SI: Make sendmsg test more strict
We want to make sure that the m0 copies are being cse'd.

llvm-svn: 237134
2015-05-12 14:18:16 +00:00
Tom Stellard
aa798340c3 R600/SI: Add VCC as an implict def of SI_KILL
When SI_KILL has a register operand, its lowered form writes to vcc.

llvm-svn: 236307
2015-05-01 03:44:09 +00:00
Tom Stellard
0b7feb1cb7 R600/SI: Fix verifier errors from the SIAnnotateControlFlow pass
This pass was generating 'Instruction does not dominate all uses!'
errors for programs which had loops with a condition variable that
depended on the result of a phi instruction from outside of the loop.

The pass was inserting new phi nodes outside of the loop which used values
defined inside the loop.

http://bugs.freedesktop.org/show_bug.cgi?id=90056

llvm-svn: 236306
2015-05-01 03:44:08 +00:00
Jan Vesely
808fff585b Reinstate revisions r234755, r234759, r234760
changes:
  Don't apply on hexagon and NVPTX since they no longer claim to support UADDO/USUBO
  Add location to getConstant
  Drop comment about the ops being turned into expand

llvm-svn: 236240
2015-04-30 17:15:56 +00:00
Tom Stellard
96301d2455 R600: Fix up for AsmPrinter's OutStreamer being a unique_ptr
Fixes a crash with basically any OpenGL application using the radeonsi
driver.

Patch by: Michel Dänzer

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90176
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 236004
2015-04-28 17:37:03 +00:00
Matt Arsenault
957bfc7458 R600: Remove / merge redundant testcases
llvm-svn: 235813
2015-04-26 00:53:33 +00:00
Matt Arsenault
5e10016f03 R600/SI: Fix verifier error when producing v_madmk_f32
Copy the kill flags when swapping the operands.

llvm-svn: 235687
2015-04-24 01:57:58 +00:00
Matthias Braun
e1a67412cf R600/RegisterCoalescer: Enable more rematerialization/add missing testcase
This enables the rematerialization of some R600 MOV instructions in the
RegisterCoalescer and adds a testcase for r235668.

llvm-svn: 235675
2015-04-24 00:25:50 +00:00
Tom Stellard
ff5cf0e1fd R600: Correctly lower CONCAT_VECTOR nodes with more than 2 operands
llvm-svn: 235662
2015-04-23 22:59:24 +00:00
Tom Stellard
8b0182af2f R600/SI: Fix indirect addressing with a negative constant offset
When the base register index of the vector plus the constant offset
was less than zero, we were passing the wrong base register to the indirect
addressing instruction.

In this case, we need to set the base register to v0 and then add
the computed (negative) index to m0.

llvm-svn: 235641
2015-04-23 20:32:01 +00:00
Matt Arsenault
deaef8e24b R600: Fix always inline pass breaking noinline functions
No test since calls are not actually supported yet.

llvm-svn: 235524
2015-04-22 17:10:44 +00:00
Tom Stellard
69a7b91e95 DAGCombine: Remove redundant NaN checks around ISD::FSQRT
This folds:

(select (setcc x, -0.0, *lt), NaN, (fsqrt x)) -> ( fsqrt x)

llvm-svn: 235333
2015-04-20 19:38:27 +00:00
Tom Stellard
d4a1950500 R600/SI: Fix verifier error caused by SIAnnotateControlFlow
This pass will always try to insert llvm.SI.ifbreak intrinsics
in the same block that its conditional value is computed in.  This is
a problem when conditions for breaks or continue are computed outside
of the loop, because the llvm.SI.ifbreak intrinsic ends up being inserted
outside of the loop.

This patch fixes this problem by inserting the llvm.SI.ifbreak
intrinsics in the loop header when the condition is computed outside
the loop.

llvm-svn: 234891
2015-04-14 14:36:45 +00:00
Jan Vesely
ffcd968647 Revert revisions r234755, r234759, r234760
Revert "Remove default in fully-covered switch (to fix Clang -Werror -Wcovered-switch-default)"
Revert "R600: Add carry and borrow instructions. Use them to implement UADDO/USUBO"
Revert "LegalizeDAG: Try to use Overflow operations when expanding ADD/SUB"

Using overflow operations fails CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll
on hexagon, nvptx, and r600. Revert while I investigate.

llvm-svn: 234768
2015-04-13 17:47:15 +00:00
Jan Vesely
d579048464 R600: Add carry and borrow instructions. Use them to implement UADDO/USUBO
v2: tighten the sub64 tests
v3: rename to CARRY/BORROW
v4: fixup test cmdline
    add known bits computation
    use sign extend instead of sub 0,x
    better add test
v5: remove redundant break
    move lowering to separate functions
    fix comments

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewers: arsenm
llvm-svn: 234759
2015-04-13 16:26:00 +00:00
Jan Vesely
a835555e40 LegalizeDAG: Try to use Overflow operations when expanding ADD/SUB
v2: consider BooleanContents when processing overflow

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewers: resistor, jholewinsky (nvidia parts)
Differential Revision: http://reviews.llvm.org/D6340

llvm-svn: 234755
2015-04-13 15:32:01 +00:00
NAKAMURA Takumi
fa88e0d2b9 llvm/test/CodeGen/R600/fminnum.ll: Relax an expression for NaN on MSVCRT like r204118.
<stdin>:202:2: note: possible intended match here
   2143289344(1.#QNAN0e+00), 2(2.802597e-45)

llvm-svn: 234719
2015-04-13 04:54:06 +00:00
Jan Vesely
452b036697 R600: Make FMIN/MAXNUM legal on all asics
v2: Add tests

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
reviewer: arsenm
llvm-svn: 234716
2015-04-12 23:45:05 +00:00
Tom Stellard
1f3416a63d R600/SI: Don't print offset0/offset1 DS operands when they are 0
llvm-svn: 234379
2015-04-08 01:09:19 +00:00
Ahmed Bougacha
91b959352c [R600/SI] Fix testcase check line.
Missing colon, instruction typo.

llvm-svn: 233414
2015-03-27 20:41:42 +00:00
Andrew Trick
43adfb30d5 Complete the MachineScheduler fix made way back in r210390.
"Fix the MachineScheduler's logic for updating ready times for in-order.
 Now the scheduler updates a node's ready time as soon as it is
 scheduled, before releasing dependent nodes."

This fix was only made in one variant of the ScheduleDAGMI driver.
Francois de Ferriere reported the issue in the other bit of code where
it was also needed.
I never got around to coming up with a test case, but it's an
obvious fix that shouldn't be delayed any longer.
I'll try to refactor this code a little better.

I did verify performance on a wide variety of targets and saw no
negative impact with this fix.

llvm-svn: 233366
2015-03-27 06:10:13 +00:00
Marek Olsak
949f5dab95 R600/SI: Select V_BFE_U32 for and+shift with a non-literal offset
llvm-svn: 233079
2015-03-24 13:40:34 +00:00
Marek Olsak
9b72868d17 R600/SI: Custom-select 32-bit S_BFE from bitwise opcodes
llvm-svn: 233078
2015-03-24 13:40:27 +00:00
Marek Olsak
63a7b084eb R600/SI: Improve BFM support
llvm-svn: 233077
2015-03-24 13:40:21 +00:00
Marek Olsak
7d77728c97 R600/SI: Use V_FRACT_F64 for faster 64-bit floor on SI
Other f64 opcodes not supported on SI can be lowered in a similar way.

v2: use complex VOP3 patterns
llvm-svn: 233076
2015-03-24 13:40:15 +00:00
Marek Olsak
43650e45c3 R600/SI: Expand fract to floor, then only select V_FRACT on CI
V_FRACT is buggy on SI.

R600-specific code is left intact.

v2: drop the multiclass, use complex VOP3 patterns
llvm-svn: 233075
2015-03-24 13:40:08 +00:00
Matt Arsenault
f5b2cd891a R600/SI: Allow commuting compares
This enables very common cases to switch to the
smaller encoding.

All of the standard LLVM canonicalizations of comparisons
are the opposite of what we want. Compares with constants
are moved to the RHS, but the first operand can be an inline
immediate, literal constant, or SGPR using the 32-bit VOPC
encoding.

There are additional bad canonicalizations that should
also be fixed, such as canonicalizing ge x, k to gt x, (k + 1)
if this makes k no longer an inline immediate value.

llvm-svn: 232988
2015-03-23 18:45:30 +00:00
Tom Stellard
f0a575f6be R600/SI: Fix crash in SIInstrInfo::areLoadsFromSameBasePtr()
This function assumed that SMRD instructions always have immediate
offsets, which is not always the case.

llvm-svn: 232957
2015-03-23 16:06:01 +00:00
Matt Arsenault
da5ece8e35 R600: Cleanup test with multiple check prefixes
llvm-svn: 232901
2015-03-21 19:15:46 +00:00
Tom Stellard
8d19f9b681 R600/SI: Add missing CHECK-LABEL lines to a test
llvm-svn: 232797
2015-03-20 03:12:42 +00:00
Rafael Espindola
242548906d Teach getDefaultFormat that we only support ELF on some architectures.
This should bring the windows bots back.

It is a bit ugly, but it is better than what we had before: The triple would
say that the object format was COFF, but llc/llvm-mc would produce an ELF.

llvm-svn: 232683
2015-03-18 22:19:16 +00:00
Rafael Espindola
ec8da3de01 Call EmitFunctionHeader just before EmitFunctionBody.
This avoids switching to .AMDGPU.config and back and hardcoding the
section it switches back to.

llvm-svn: 232479
2015-03-17 14:34:42 +00:00
Tom Stellard
7c840bcbf3 R600/SI: don't try min3/max3/med3 with f64
There are no opcodes for this. This also adds a test case.

v2: make test more robust

Patch by: Grigori Goronzy

llvm-svn: 232386
2015-03-16 15:53:55 +00:00
David Blaikie
f72d05bc7b [opaque pointer type] Add textual IR support for explicit type parameter to gep operator
Similar to gep (r230786) and load (r230794) changes.

Similar migration script can be used to update test cases, which
successfully migrated all of LLVM and Polly, but about 4 test cases
needed manually changes in Clang.

(this script will read the contents of stdin and massage it into stdout
- wrap it in the 'apply.sh' script shown in previous commits + xargs to
apply it over a large set of test cases)

import fileinput
import sys
import re

rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL)

def conv(match):
  line = match.group(1)
  line += match.group(4)
  line += ", "
  line += match.group(2)
  return line

line = sys.stdin.read()
off = 0
for match in re.finditer(rep, line):
  sys.stdout.write(line[off:match.start()])
  sys.stdout.write(conv(match))
  off = match.end()
sys.stdout.write(line[off:])

llvm-svn: 232184
2015-03-13 18:20:45 +00:00
Matt Arsenault
314eac7477 R600/SI: Add test for min / max with immediate
Make sure this isn't getting confused by canonicalizations
of comparisons with a constant.

llvm-svn: 232177
2015-03-13 16:43:48 +00:00
Tom Stellard
c0503926f5 R600/SI: Remove _e32 and _e64 suffixes from mnemonics
Instead print them as part of the $dst operand.  The AsmMatcher
requires the 32-bit and 64-bit encodings have the same mnemonic in
order to parse them correctly.

llvm-svn: 232105
2015-03-12 21:34:22 +00:00
Marek Olsak
4d00dd2b93 R600/SI: Limit SGPRs to 80 on Tonga and Iceland
This is a candidate for stable.

llvm-svn: 231659
2015-03-09 15:48:09 +00:00
Matthias Braun
898d11e864 DAGCombiner: Canonicalize select(and/or,x,y) depending on target.
This is based on the following equivalences:
select(C0 & C1, X, Y) <=> select(C0, select(C1, X, Y), Y)
select(C0 | C1, X, Y) <=> select(C0, X, select(C1, X, Y))

Many target cannot perform and/or on the CPU flags and therefore the
right side should be choosen to avoid materializign the i1 flags in an
integer register. If the target can perform this operation efficiently
we normalize to the left form.

Differential Revision: http://reviews.llvm.org/D7622

llvm-svn: 231507
2015-03-06 19:49:10 +00:00
Marek Olsak
d2af89df10 R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32
Required by OpenGL (ARB_gpu_shader5).

llvm-svn: 231259
2015-03-04 17:33:45 +00:00
David Blaikie
a79ac14fa6 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794
2015-02-27 21:17:42 +00:00
David Blaikie
79e6c74981 [opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction
One of several parallel first steps to remove the target type of pointers,
replacing them with a single opaque pointer type.

This adds an explicit type parameter to the gep instruction so that when the
first parameter becomes an opaque pointer type, the type to gep through is
still available to the instructions.

* This doesn't modify gep operators, only instructions (operators will be
  handled separately)

* Textual IR changes only. Bitcode (including upgrade) and changing the
  in-memory representation will be in separate changes.

* geps of vectors are transformed as:
    getelementptr <4 x float*> %x, ...
  ->getelementptr float, <4 x float*> %x, ...
  Then, once the opaque pointer type is introduced, this will ultimately look
  like:
    getelementptr float, <4 x ptr> %x
  with the unambiguous interpretation that it is a vector of pointers to float.

* address spaces remain on the pointer, not the type:
    getelementptr float addrspace(1)* %x
  ->getelementptr float, float addrspace(1)* %x
  Then, eventually:
    getelementptr float, ptr addrspace(1) %x

Importantly, the massive amount of test case churn has been automated by
same crappy python code. I had to manually update a few test cases that
wouldn't fit the script's model (r228970,r229196,r229197,r229198). The
python script just massages stdin and writes the result to stdout, I
then wrapped that in a shell script to handle replacing files, then
using the usual find+xargs to migrate all the files.

update.py:
import fileinput
import sys
import re

ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
normrep = re.compile(       r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")

def conv(match, line):
  if not match:
    return line
  line = match.groups()[0]
  if len(match.groups()[5]) == 0:
    line += match.groups()[2]
  line += match.groups()[3]
  line += ", "
  line += match.groups()[1]
  line += "\n"
  return line

for line in sys.stdin:
  if line.find("getelementptr ") == line.find("getelementptr inbounds"):
    if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("):
      line = conv(re.match(ibrep, line), line)
  elif line.find("getelementptr ") != line.find("getelementptr ("):
    line = conv(re.match(normrep, line), line)
  sys.stdout.write(line)

apply.sh:
for name in "$@"
do
  python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name"
  rm -f "$name.tmp"
done

The actual commands:
From llvm/src:
find test/ -name *.ll | xargs ./apply.sh
From llvm/src/tools/clang:
find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}"
From llvm/src/tools/polly:
find test/ -name *.ll | xargs ./apply.sh

After that, check-all (with llvm, clang, clang-tools-extra, lld,
compiler-rt, and polly all checked out).

The extra 'rm' in the apply.sh script is due to a few files in clang's test
suite using interesting unicode stuff that my python script was throwing
exceptions on. None of those files needed to be migrated, so it seemed
sufficient to ignore those cases.

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7636

llvm-svn: 230786
2015-02-27 19:29:02 +00:00
Tom Stellard
eb05c610b4 R600/SI: Remove M0 from DS assembly strings
This matches the assembly syntax for the proprietary compiler.

llvm-svn: 230645
2015-02-26 17:08:43 +00:00
Tom Stellard
ecc419c31d R600/SI: Remove isel mubuf legalization
We legalize mubuf instructions post-instruction selection, so this
code is no longer needed.

llvm-svn: 230352
2015-02-24 17:59:19 +00:00
Matt Arsenault
f07833057c R600/SI: Use v_madmk_f32
llvm-svn: 230149
2015-02-21 21:29:10 +00:00