Chris Lattner
c5e1312baa
Use a more efficient method of creating integer and float virtual registers
...
(avoids an extra level of indirection in MakeReg).
defined MakeIntReg using RegMap->createVirtualRegister(PPC32::GPRCRegisterClass)
defined MakeFPReg using RegMap->createVirtualRegister(PPC32::FPRCRegisterClass)
s/MakeReg(MVT::i32)/MakeIntReg/
s/MakeReg(MVT::f64)/MakeFPReg/
Patch by Jim Laskey!
llvm-svn: 22759
2005-08-11 17:15:31 +00:00
Nate Begeman
5646b181e8
Make SELECT illegal on PPC32, switch to using SELECT_CC, which more closely
...
reflects what the hardware is capable of. This significantly simplifies
the CC handling logic throughout the ISel.
llvm-svn: 22756
2005-08-10 20:52:09 +00:00
Chris Lattner
3428b95634
Changes for PPC32ISelPattern.cpp
...
1. Clean up how SelectIntImmediateExpr handles use counts.
2. "Subtract from" was not clearing hi 16 bits.
Patch by Jim Laskey
llvm-svn: 22754
2005-08-10 18:11:33 +00:00
Chris Lattner
aeedcc7fc2
Changed the XOR case to use the isOprNot predicate.
...
Patch by Jim Laskey!
llvm-svn: 22750
2005-08-10 16:35:46 +00:00
Chris Lattner
67d0753773
1. Refactored handling of integer immediate values for add, or, xor and sub.
...
New routine: ISel::SelectIntImmediateExpr
2. Now checking use counts of large constants. If use count is > 2 then drop
thru so that the constant gets loaded into a register.
Source:
int %test1(int %a) {
entry:
%tmp.1 = add int %a, 123456789 ; <int> [#uses=1]
%tmp.2 = or int %tmp.1, 123456789 ; <int> [#uses=1]
%tmp.3 = xor int %tmp.2, 123456789 ; <int> [#uses=1]
%tmp.4 = sub int %tmp.3, -123456789 ; <int> [#uses=1]
ret int %tmp.4
}
Did Emit:
.machine ppc970
.text
.align 2
.globl _test1
_test1:
.LBB_test1_0: ; entry
addi r2, r3, -13035
addis r2, r2, 1884
ori r2, r2, 52501
oris r2, r2, 1883
xori r2, r2, 52501
xoris r2, r2, 1883
addi r2, r2, 52501
addis r3, r2, 1883
blr
Now Emits:
.machine ppc970
.text
.align 2
.globl _test1
_test1:
.LBB_test1_0: ; entry
lis r2, 1883
ori r2, r2, 52501
add r3, r3, r2
or r3, r3, r2
xor r3, r3, r2
add r3, r3, r2
blr
Patch by Jim Laskey!
llvm-svn: 22749
2005-08-10 16:34:52 +00:00
Chris Lattner
5f56d71cd7
Fix a bug compiling: select (i32 < i32), f32, f32
...
llvm-svn: 22747
2005-08-10 03:40:09 +00:00
Chris Lattner
6ec7745e80
Update the targets to the new SETCC/CondCodeSDNode interfaces.
...
llvm-svn: 22729
2005-08-09 20:21:10 +00:00
Chris Lattner
2035c4f7f8
Minor cleanup patch, no functionality changes. Written by Jim Laskey.
...
llvm-svn: 22727
2005-08-09 18:29:55 +00:00
Chris Lattner
4c62c647c2
Fix CodeGen/Generic/div-neg-power-2.ll, a regression from last night.
...
llvm-svn: 22726
2005-08-09 18:08:41 +00:00
Nate Begeman
c92787e1f5
Factor out some common code, and be smarter about when to emit load hi/lo
...
code sequences.
llvm-svn: 22719
2005-08-08 22:22:56 +00:00
Chris Lattner
64068eb7da
Remove getImmediateForOpcode, which is now dead.
...
Patch by Jim Laskey.
llvm-svn: 22716
2005-08-08 21:34:13 +00:00
Chris Lattner
25388199a2
Add new immediate handling support for mul/div.
...
Patch by Jim Laskey!
llvm-svn: 22715
2005-08-08 21:33:23 +00:00
Chris Lattner
8e9dc31928
Add support for OR/XOR/SUB immediates that are handled with the new immediate
...
way. This allows ORI/ORIS pairs, for example.
llvm-svn: 22714
2005-08-08 21:30:29 +00:00
Chris Lattner
fd0fe76ba6
Modify the ISD::AND opcode case to use new immediate constant predicates.
...
Includes wider support for rotate and mask cases.
Patch by Jim Laskey.
I've requested that Jim add new regression tests the newly handled cases.
llvm-svn: 22712
2005-08-08 21:24:57 +00:00
Chris Lattner
81e0e3e933
Modify the ISD::ADD opcode case to use new immediate constant predicates.
...
Includes support for 32-bit constants using addi/addis.
Patch by Jim Laskey.
llvm-svn: 22711
2005-08-08 21:21:03 +00:00
Chris Lattner
4c54dae243
Modify existing support functions to use new immediate constant predicates.
...
Patch by Jim Laskey
llvm-svn: 22710
2005-08-08 21:12:35 +00:00
Chris Lattner
3cc070cc36
Add support predicates for future immediate constant changes.
...
Patch by Jim Laskey
llvm-svn: 22709
2005-08-08 21:10:27 +00:00
Chris Lattner
f2267ed5c5
Move IsRunOfOnes to a more logical place and rename to a proper predicate form
...
(lowercase isXXX).
Patch by Jim Laskey.
llvm-svn: 22708
2005-08-08 21:08:09 +00:00
Chris Lattner
983a415b6a
Consolidate the GPOpt stuff to all use the Subtarget, instead of still
...
depending on the command line option. Now the command line option just
sets the subtarget as appropriate. G5 opts will now default to on on
G5-enabled nightly testers among other machines.
llvm-svn: 22688
2005-08-05 22:05:03 +00:00
Misha Brukman
fce3285891
Fix grammar: apostrophe-s ('s) is possessive, not plural; also iff vs. if.
...
llvm-svn: 22619
2005-08-03 17:29:52 +00:00
Chris Lattner
8dc82b7909
minor capitalization thing, patch by Jim Laskey
...
llvm-svn: 22617
2005-08-03 16:52:22 +00:00
Chris Lattner
989d8bbda9
This hunk accidentally got dropped. Patch by Jim Laskey
...
llvm-svn: 22595
2005-08-02 19:30:55 +00:00
Chris Lattner
6667bdbaca
Update to use the new MathExtras.h support for log2 computation.
...
Patch contributed by Jim Laskey!
llvm-svn: 22594
2005-08-02 19:26:06 +00:00
Chris Lattner
c98d48fabe
add a pass name to make debugging dumps nicer
...
llvm-svn: 22588
2005-08-02 19:07:49 +00:00
Chris Lattner
a8195603e4
Eliminate an extra copy from R1 that Nate noticed on function calls that
...
have to write arguments to the stack
llvm-svn: 22536
2005-07-28 05:23:43 +00:00
Chris Lattner
7c38bd14ef
Specify the correct number of operands
...
llvm-svn: 22535
2005-07-28 04:42:11 +00:00
Nate Begeman
c5b6bd9a8e
Fold constant adds into loads and stores to frame indices.
...
For the following code:
double %ext(int %A.0__, long %A.1__) {
%A_addr = alloca %typedef.DComplex ; <%typedef.DComplex*> [#uses=2]
%tmp.1 = cast %typedef.DComplex* %A_addr to int* ; <int*> [#uses=1]
store int %A.0__, int* %tmp.1
%tmp.2 = getelementptr %typedef.DComplex* %A_addr, int 0, uint 1 ; <double*> [#uses=2]
%tmp.3 = cast double* %tmp.2 to long* ; <long*> [#uses=1]
store long %A.1__, long* %tmp.3
%tmp.5 = load double* %tmp.2 ; <double> [#uses=1]
ret double %tmp.5
}
We now generate:
_ext:
.LBB_ext_0: ;
stw r3, -12(r1)
stw r4, -8(r1)
stw r5, -4(r1)
lfd f1, -8(r1)
blr
Instead of:
_ext:
.LBB_ext_0: ;
stw r3, -12(r1)
addi r2, r1, -12
stw r4, 4(r2)
stw r5, 8(r2)
lfd f1, 4(r2)
blr
This also fires hundreds of times on MultiSource.
llvm-svn: 22533
2005-07-28 03:02:05 +00:00
Nate Begeman
594a3ba40e
Fix some comments
...
llvm-svn: 22530
2005-07-27 23:11:27 +00:00
Jeff Cohen
5f4ef3c5a8
Eliminate all remaining tabs and trailing spaces.
...
llvm-svn: 22523
2005-07-27 06:12:32 +00:00
Nate Begeman
b9ce12b4bb
Fix an optimization put in for accessing static globals. This obviates
...
the need to build PIC.
llvm-svn: 22512
2005-07-25 21:15:28 +00:00
Chris Lattner
12f5d12b21
PowerPC no-pic code is not quite ready for prime-time
...
llvm-svn: 22507
2005-07-22 22:58:34 +00:00
Nate Begeman
a9443f29b0
Support building non-PIC
...
Remove the LoadHiAddr pseudo-instruction.
Optimization of stores to and loads from statics.
Force JIT to use new non-PIC codepaths.
llvm-svn: 22494
2005-07-21 20:44:43 +00:00
Nate Begeman
8465fe8b4b
Generate mfocrf when targeting g5. Generate fsqrt/fsqrts when targetin g5.
...
8-byte align doubles.
llvm-svn: 22486
2005-07-20 22:42:00 +00:00
Nate Begeman
0851f1aaa1
Integrate SelectFPExpr into SelectExpr. This gets PPC32 closer to being
...
automatically generated from a target description.
llvm-svn: 22470
2005-07-19 16:51:05 +00:00
Chris Lattner
53676dfd33
Change *EXTLOAD to use an VTSDNode operand instead of being an MVTSDNode.
...
This is the last MVTSDNode.
This allows us to eliminate a bunch of special case code for handling
MVTSDNodes.
Also, remove some uses of dyn_cast that should really be cast (which is
cheaper in a release build).
llvm-svn: 22368
2005-07-10 01:56:13 +00:00
Chris Lattner
36db1ed06f
Change TRUNCSTORE to use a VTSDNode operand instead of being an MVTSTDNode
...
llvm-svn: 22366
2005-07-10 00:29:18 +00:00
Chris Lattner
a7220851c0
Make several cleanups to Andrews varargs change:
...
1. Pass Value*'s into lowering methods so that the proper pointers can be
added to load/stores from the valist
2. Intrinsics that return void should only return a token chain, not a token
chain/retval pair.
3. Rename LowerVAArgNext -> LowerVAArg, because VANext is long gone.
4. Now that we have Value*'s available in the lowering methods, pass them
into any load/stores from the valist that are emitted
llvm-svn: 22339
2005-07-05 19:58:54 +00:00
Chris Lattner
1239d2d7ff
Fix PowerPC varargs
...
llvm-svn: 22335
2005-07-05 17:48:31 +00:00
Chris Lattner
d313b92b66
Varargs is apparently currently broken on PPC. This hacks it so that it
...
is at least overloading the right virtual methods. The implementations
are currently wrong though. This fixes Ptrdist/bc, but not other programs
(e.g. siod).
llvm-svn: 22326
2005-07-01 23:11:56 +00:00
Nate Begeman
1bf8927518
Commit fix for generating conditional branch pseudo instructions that
...
avoids dereferencing the end() iterator when selecting the fallthrough
block. This requires an ilist change.
llvm-svn: 22212
2005-06-15 18:22:43 +00:00
Nate Begeman
54c022156d
Commit a small improvement that is already in the x86 and ia64 backends to
...
not generate unnecessary register copies. This improves compile time by
2-5% depending on the test.
llvm-svn: 22210
2005-06-14 03:55:23 +00:00
Nate Begeman
60cf00c982
Handle some more real world cases of rlwimi. These don't come up that
...
regularly in "normal" code, but for things like software graphics, they
make a big difference.
For the following code:
unsigned short Trans16Bit(unsigned srcA,unsigned srcB,unsigned alpha)
{
unsigned tmpA,tmpB,mixed;
tmpA = ((srcA & 0x03E0) << 15) | (srcA & 0x7C1F);
tmpB = ((srcB & 0x03E0) << 15) | (srcB & 0x7C1F);
mixed = (tmpA * alpha) + (tmpB * (32 - alpha));
return ((mixed >> 5) & 0x7C1F) | ((mixed >> 20) & 0x03E0);
}
We now generate:
_Trans16Bit:
.LBB_Trans16Bit_0: ; entry
andi. r2, r4, 31775
rlwimi r2, r4, 15, 7, 11
subfic r4, r5, 32
mullw r2, r2, r4
andi. r4, r3, 31775
rlwimi r4, r3, 15, 7, 11
mullw r3, r4, r5
add r2, r2, r3
srwi r3, r2, 5
andi. r3, r3, 31775
rlwimi r3, r2, 12, 22, 26
blr
Instead of:
_Trans16Bit:
.LBB_Trans16Bit_0: ; entry
slwi r2, r4, 15
rlwinm r2, r2, 0, 7, 11
andi. r4, r4, 31775
or r2, r2, r4
subfic r4, r5, 32
mullw r2, r2, r4
slwi r4, r3, 15
rlwinm r4, r4, 0, 7, 11
andi. r3, r3, 31775
or r3, r4, r3
mullw r3, r3, r5
add r2, r2, r3
srwi r3, r2, 5
andi. r3, r3, 31775
srwi r2, r2, 20
rlwimi r3, r2, 0, 22, 26
blr
llvm-svn: 22201
2005-06-08 04:14:27 +00:00
Chris Lattner
0ae9b08916
Fix andrews changes to fit in 80 columns
...
llvm-svn: 22064
2005-05-15 19:54:37 +00:00
Chris Lattner
8abab9b0c7
treat TAILCALL nodes identically to CALL nodes
...
llvm-svn: 21977
2005-05-13 20:29:26 +00:00
Chris Lattner
2e77db6af6
Add an isTailCall flag to LowerCallTo
...
llvm-svn: 21958
2005-05-13 18:50:42 +00:00
Chris Lattner
6756f2f795
Realize that we don't support fmod directly, fixing CodeGen/Generic/print-arith-fp.ll
...
llvm-svn: 21939
2005-05-13 16:20:22 +00:00
Chris Lattner
2dce703710
rename the ADJCALLSTACKDOWN/ADJCALLSTACKUP nodes to be CALLSEQ_START/BEGIN.
...
llvm-svn: 21915
2005-05-12 23:24:06 +00:00
Chris Lattner
36674a123e
Pass in Calling Convention to use into LowerCallTo
...
llvm-svn: 21899
2005-05-12 19:56:45 +00:00
Chris Lattner
f80969f29b
These targets don't like setcc
...
llvm-svn: 21884
2005-05-12 02:06:00 +00:00
Nate Begeman
99fa5bc1fa
Necessary changes to codegen cttz efficiently on PowerPC
...
1. Teach LegalizeDAG how to better legalize CTTZ if the target doesn't have
CTPOP, but does have CTLZ
2. Teach PPC32 how to do sub x, const -> add x, -const for valid consts
3. Teach PPC32 how to do and (xor a, -1) b -> andc b, a
4. Teach PPC32 that ISD::CTLZ -> PPC::CNTLZW
llvm-svn: 21880
2005-05-11 23:43:56 +00:00