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393 Commits

Author SHA1 Message Date
Bob Wilson
3b51560ae4 Revise ARM inline assembly memory operands to require the memory address to 
be in a register.  The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb.  Radar 7137468.

llvm-svn: 84022
 2009-10-13 20:50:28 +00:00
Sandeep Patel
423e42b371 Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. 
llvm-svn: 84009
 2009-10-13 18:59:48 +00:00
Benjamin Kramer
258c7fa33a Eliminate some redundant llvm-as calls. 
llvm-svn: 83837
 2009-10-12 09:31:55 +00:00
Dan Gohman
50998f4584 Update this test; the code is the same but it gets counted as one 
fewer remat.

llvm-svn: 83690
 2009-10-09 23:31:04 +00:00
Bob Wilson
35b6173a17 Merge a bunch of NEON tests into larger files so they run faster. 
llvm-svn: 83667
 2009-10-09 20:20:54 +00:00
Bob Wilson
6dd3b9ad58 Convert some ARM tests with lots of greps to use FileCheck. 
llvm-svn: 83651
 2009-10-09 17:20:46 +00:00
Bob Wilson
e9b19f76cb Commit one last NEON test to use FileCheck. That's all of them now! 
llvm-svn: 83617
 2009-10-09 05:31:56 +00:00
Bob Wilson
24b84fecf2 Convert more NEON tests to use FileCheck. 
llvm-svn: 83616
 2009-10-09 05:14:48 +00:00
Bob Wilson
84e7967fae Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. 
llvm-svn: 83600
 2009-10-09 00:01:36 +00:00
Bob Wilson
c409030838 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. 
llvm-svn: 83598
 2009-10-08 23:51:31 +00:00
Bob Wilson
b851eb356a Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. 
llvm-svn: 83596
 2009-10-08 23:38:24 +00:00
Bob Wilson
1fd98d67e3 Convert more NEON tests to use FileCheck. 
llvm-svn: 83595
 2009-10-08 23:33:03 +00:00
Bob Wilson
38ba47225a Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. 
Also fix some copy-and-paste errors in previous changes.

llvm-svn: 83590
 2009-10-08 22:53:57 +00:00
Bob Wilson
f448255063 Convert more NEON tests to use FileCheck. 
llvm-svn: 83587
 2009-10-08 22:33:53 +00:00
Bob Wilson
cf54e934f8 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. 
llvm-svn: 83585
 2009-10-08 22:27:33 +00:00
Anton Korobeynikov
222b86cd54 Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair. 
llvm-svn: 83572
 2009-10-08 20:43:22 +00:00
Bob Wilson
c2728f44a9 Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. 
llvm-svn: 83568
 2009-10-08 18:56:10 +00:00
Bob Wilson
7d94eb4722 Convert more NEON tests to use FileCheck. 
llvm-svn: 83528
 2009-10-08 06:02:10 +00:00
Bob Wilson
b6b0ab6117 Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors. 
llvm-svn: 83526
 2009-10-08 05:18:18 +00:00
Bob Wilson
71387b4b2f Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83518
 2009-10-08 00:28:28 +00:00
Bob Wilson
d4f5670096 Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83513
 2009-10-08 00:21:01 +00:00
Bob Wilson
32cc4ec304 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors. 
llvm-svn: 83508
 2009-10-07 23:54:04 +00:00
Bob Wilson
d1de3b82ff Convert more NEON tests to use FileCheck. 
llvm-svn: 83507
 2009-10-07 23:47:21 +00:00
Bob Wilson
5ef3c6d9f4 Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83506
 2009-10-07 23:39:57 +00:00
Bob Wilson
763be1a248 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83502
 2009-10-07 22:57:01 +00:00
Bob Wilson
6d850f294d Convert more NEON tests to use FileCheck. 
llvm-svn: 83497
 2009-10-07 22:30:19 +00:00
Bob Wilson
70f004d9e6 Convert test to FileCheck. 
llvm-svn: 83487
 2009-10-07 20:51:42 +00:00
Bob Wilson
e7ef4a9a6b Add codegen support for NEON vst4 intrinsics with 128-bit vectors. 
llvm-svn: 83486
 2009-10-07 20:49:18 +00:00
Bob Wilson
23464866ad Add codegen support for NEON vst3 intrinsics with 128-bit vectors. 
llvm-svn: 83484
 2009-10-07 20:30:08 +00:00
Bob Wilson
3dcb5377ef Add codegen support for NEON vst2 intrinsics with 128-bit vectors. 
llvm-svn: 83482
 2009-10-07 18:47:39 +00:00
Bob Wilson
ab3a9474d6 Add codegen support for NEON vld4 intrinsics with 128-bit vectors. 
llvm-svn: 83479
 2009-10-07 18:09:32 +00:00
Bob Wilson
6bbefc2f67 Add codegen support for NEON vld3 intrinsics with 128-bit vectors. 
llvm-svn: 83471
 2009-10-07 17:24:55 +00:00
Bob Wilson
aa47a8d71a Add tests for vld2 of 128-bit vectors. 
llvm-svn: 83468
 2009-10-07 17:19:13 +00:00
Bob Wilson
3251776d1d Update NEON struct names to match llvm-gcc changes. 
(This is not required for correctness but might help with sanity.)

llvm-svn: 83415
 2009-10-06 21:16:19 +00:00
Evan Cheng
4ad726b4be Fix tests. 
llvm-svn: 83241
 2009-10-02 06:53:57 +00:00
Evan Cheng
2dcee28a61 Move load / store multiple before post-alloc scheduling. 
llvm-svn: 83236
 2009-10-02 04:57:15 +00:00
David Goodwin
1cc6dd97da Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default. 
llvm-svn: 83218
 2009-10-01 22:19:57 +00:00
David Goodwin
9a051a5922 Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string. 
llvm-svn: 83215
 2009-10-01 21:46:35 +00:00
David Goodwin
17199b56b0 Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. 
llvm-svn: 83122
 2009-09-30 00:10:16 +00:00
David Goodwin
bef958c716 Post-RA regressions. 
llvm-svn: 83075
 2009-09-29 17:10:26 +00:00
Evan Cheng
139c3dba53 Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat. 
llvm-svn: 83058
 2009-09-29 07:07:30 +00:00
Evan Cheng
e0c5313493 Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg of 
physical registers. This is especially critical for the later two since they
start the live interval of a super-register. e.g.
%DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
If this instruction is eliminated, the register scavenger will not be happy as
D0 is not defined previously.
This fixes PR5055.

llvm-svn: 82968
 2009-09-28 05:28:43 +00:00
Anton Korobeynikov
7c2b1e71c1 Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. 
This should be better than single load from constpool.

llvm-svn: 82948
 2009-09-27 23:52:58 +00:00
Evan Cheng
cf2a9c9962 Remove this test. 
llvm-svn: 82869
 2009-09-26 18:51:37 +00:00
Daniel Dunbar
ccde96e96b "Update" tests for -disable-if-conversion removal. I think branch.ll should just 
be removed, but I XFAIL'd it for now.

llvm-svn: 82847
 2009-09-26 05:29:36 +00:00
Evan Cheng
d080f7bf26 Convert test to filecheck. 
llvm-svn: 82835
 2009-09-26 02:41:17 +00:00
Evan Cheng
3872b3c13e Flip -disable-post-RA-scheduler to -post-RA-scheduler. 
llvm-svn: 82803
 2009-09-25 21:38:11 +00:00
Dan Gohman
48b185d6f7 Improve MachineMemOperand handling. 
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.

llvm-svn: 82794
 2009-09-25 20:36:54 +00:00
Bob Wilson
d60367c198 pr4926: ARM requires the stack pointer to be aligned, even for leaf functions. 
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned.  For the older ARM APCS ABI, the stack
alignment is just always 4 bytes.  For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.

After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo.  This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4.  (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.

llvm-svn: 82767
 2009-09-25 14:41:49 +00:00
Bob Wilson
6cd4aee5e9 Convert to FileCheck. 
llvm-svn: 82710
 2009-09-24 20:23:02 +00:00