caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
84,791 Commits 1 Branch 0 Tags
caa710dfd236bb2fa8aec42808aee2cef9ed99a8
Commit Graph

384 Commits

Author SHA1 Message Date
Dale Johannesen
81ef35b3ca Improvements to tail call code. No functional effect 
unless using -arm-tail-calls.

llvm-svn: 105515
 2010-06-05 00:51:39 +00:00
Dale Johannesen
d1b9311afa More thoroughly disable tails calls by default. 
8060143, although this doesn't fix the real problem with tail call.

llvm-svn: 105472
 2010-06-04 18:04:24 +00:00
Bob Wilson
d8a9a04739 For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and 
VECTOR_SHUFFLEs to REG_SEQUENCE instructions.  The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized.  That is pretty awful, but I guess it
makes sense for other targets.  Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.

llvm-svn: 105439
 2010-06-04 00:04:02 +00:00
Dale Johannesen
d679ff7330 Early implementation of tail call for ARM. 
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.

llvm-svn: 105413
 2010-06-03 21:09:53 +00:00
Jim Grosbach
84511e1526 Clean up 80 column violations. No functional change. 
llvm-svn: 105350
 2010-06-02 21:53:11 +00:00
Evan Cheng
bf91499f1a Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions. 
llvm-svn: 105060
 2010-05-28 23:25:23 +00:00
Jim Grosbach
faa3abbe39 Update the saved stack pointer in the sjlj function context following either 
an alloca() or an llvm.stackrestore(). rdar://8031573

llvm-svn: 104900
 2010-05-27 23:49:24 +00:00
Jim Grosbach
c9f532dddc back out 104862/104869. Can reuse stacksave after all. Very cool. 
llvm-svn: 104897
 2010-05-27 23:11:57 +00:00
Jim Grosbach
5cde219fb1 add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH 
to update the jmpbuf in the presence of VLAs.

llvm-svn: 104862
 2010-05-27 18:23:48 +00:00
Jim Grosbach
c98892fdaa Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in 
ISD::. No functional change.

llvm-svn: 104734
 2010-05-26 20:22:18 +00:00
Bob Wilson
26fdebcae9 Clean up indentation. 
llvm-svn: 104580
 2010-05-25 03:36:52 +00:00
Evan Cheng
755d45be43 LR is in GPR, not tGPR even in Thumb1 mode. 
llvm-svn: 104518
 2010-05-24 18:00:18 +00:00
Bob Wilson
49f40e8c32 VDUP doesn't support vectors with 64-bit elements. 
llvm-svn: 104455
 2010-05-23 05:42:31 +00:00
Evan Cheng
168ced94d8 Implement @llvm.returnaddress. rdar://8015977. 
llvm-svn: 104421
 2010-05-22 01:47:14 +00:00
Jim Grosbach
bd9485db63 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. 
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419
 2010-05-22 01:06:18 +00:00
Bob Wilson
91fdf68516 Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by 
copying VFP subregs.  This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.

llvm-svn: 104415
 2010-05-22 00:23:12 +00:00
Evan Cheng
34c260458a Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float). 
llvm-svn: 104307
 2010-05-21 00:43:17 +00:00
Evan Cheng
4401f8873c Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. 
llvm-svn: 104293
 2010-05-20 23:26:43 +00:00
Bob Wilson
5954994bba Handle Neon v2f64 and v2i64 vector shuffles as register copies. 
This fixes the remaining issue with pr7167.

llvm-svn: 104257
 2010-05-20 18:39:53 +00:00
Evan Cheng
738e920edf Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace. 
llvm-svn: 104147
 2010-05-19 20:19:50 +00:00
Evan Cheng
f19384d54a Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 
llvm-svn: 104060
 2010-05-18 21:31:17 +00:00
Anton Korobeynikov
4c719c4515 Generalize the ARM DAG combiner of mul with constants to all power-of-two cases. 
llvm-svn: 103901
 2010-05-16 08:54:20 +00:00
Anton Korobeynikov
1bf28a128b Some cheap DAG combine goodness for multiplication with a particular constant. 
This can be extended later on to handle more "complex" constants.

llvm-svn: 103881
 2010-05-15 18:16:59 +00:00
Evan Cheng
3d214cdfaf v4i64 and v8i64 are only synthesizable when NEON is available. 
llvm-svn: 103855
 2010-05-15 02:20:21 +00:00
Evan Cheng
4cad68eb34 Allow TargetLowering::getRegClassFor() to be called on illegal types. Also 
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.

llvm-svn: 103854
 2010-05-15 02:18:07 +00:00
Evan Cheng
cd67c21407 Added a QQQQ register file to model 4-consecutive Q registers. 
llvm-svn: 103760
 2010-05-14 02:13:41 +00:00
Dan Gohman
bb919dfb6b Implement a bunch more TargetSelectionDAGInfo infrastructure. 
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.

llvm-svn: 103481
 2010-05-11 17:31:57 +00:00
Evan Cheng
2fa5a7e7e4 Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. 
llvm-svn: 103459
 2010-05-11 07:26:32 +00:00
Evan Cheng
c2ae5f546f Model vld2 / vst2 with reg_sequence. 
llvm-svn: 103411
 2010-05-10 17:34:18 +00:00
Jim Grosbach
2a41cad900 Clean up the conditional for handling of sign_extend_inreg based on 
whether the extract instructions are available.

rdar://7956878

llvm-svn: 103277
 2010-05-07 18:34:55 +00:00
Jim Grosbach
151cd8f159 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack 
instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136
 2010-05-05 23:44:43 +00:00
Jim Grosbach
92d999001c Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by 
Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.

llvm-svn: 103119
 2010-05-05 20:44:35 +00:00
Evan Cheng
d85631e700 Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE. 
llvm-svn: 103104
 2010-05-05 18:28:36 +00:00
Dan Gohman
25c1653700 Get rid of the EdgeMapping map. Instead, just check for BasicBlock 
changes before doing phi lowering for switches.

llvm-svn: 102809
 2010-05-01 00:01:06 +00:00
Dan Gohman
21cea8ac2e Use const qualifiers with TargetLowering. This eliminates several 
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635
 2010-04-17 15:26:15 +00:00
Dan Gohman
31ae586c74 Move per-function state out of TargetLowering subclasses and into 
MachineFunctionInfo subclasses.

llvm-svn: 101634
 2010-04-17 14:41:14 +00:00
Bob Wilson
59b70eacad Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this 
may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.

llvm-svn: 101615
 2010-04-17 05:30:19 +00:00
Evan Cheng
f7f97b4bbd Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2. 
llvm-svn: 101410
 2010-04-15 22:20:34 +00:00
Anders Carlsson
47bccf7f28 Fix build. 
llvm-svn: 101335
 2010-04-15 03:11:28 +00:00
Dan Gohman
bcaf681cde Add const qualifiers to CodeGen's use of LLVM IR constructs. 
llvm-svn: 101334
 2010-04-15 01:51:59 +00:00
Jim Grosbach
32bb362655 Add -arm-long-calls option to force calls to be indirect. This makes the 
kernel linker happier when dealing with kexts.

Radar 7805069

llvm-svn: 101303
 2010-04-14 22:28:31 +00:00
Bob Wilson
c05b887c84 Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand 
does not have a legal type.  The legalizer does not know how to handle those
nodes.  Radar 7854640.

llvm-svn: 101282
 2010-04-14 20:45:23 +00:00
Bob Wilson
699bdf7adf Handle a v2f64 formal parameter that is split between registers and memory 
such that the entire second half is in memory.  Radar 7855014.

llvm-svn: 101181
 2010-04-13 22:03:22 +00:00
Bob Wilson
5202269dc4 Expand SELECT and SELECT_CC for NEON vector types. 
Radar 7770501.

llvm-svn: 100568
 2010-04-06 22:02:24 +00:00
Mon P Wang
c576ee9040 Reapply address space patch after fixing an issue in MemCopyOptimizer. 
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)

llvm-svn: 100304
 2010-04-04 03:10:48 +00:00
Mon P Wang
999c1b927b Revert r100191 since it breaks objc in clang 
llvm-svn: 100199
 2010-04-02 18:43:02 +00:00
Mon P Wang
a972ab8564 Reapply address space patch after fixing an issue in MemCopyOptimizer. 
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)

llvm-svn: 100191
 2010-04-02 18:04:15 +00:00
Bob Wilson
6f7fd28824 Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots. 
llvm-svn: 99948
 2010-03-30 22:27:04 +00:00
Mon P Wang
7460571381 Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset, 
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.

llvm-svn: 99928
 2010-03-30 20:55:56 +00:00
Jim Grosbach
07607382d8 tweak the arm if conversion heuristic 
llvm-svn: 99402
 2010-03-24 16:15:14 +00:00