Evan Cheng
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cc2efe11db
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Fix some latency computation bugs: if the use is not a machine opcode do not just return zero.
llvm-svn: 105061
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2010-05-28 23:26:21 +00:00 |
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Evan Cheng
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34c260458a
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Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
llvm-svn: 104307
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2010-05-21 00:43:17 +00:00 |
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Jakob Stoklund Olesen
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e11cdf8cc8
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TwoAddressInstructionPass doesn't really know how to merge live intervals when
lowering REG_SEQUENCE instructions.
Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.
llvm-svn: 104146
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2010-05-19 20:08:00 +00:00 |
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Evan Cheng
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e7fc64a5c9
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Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.
llvm-svn: 104050
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2010-05-18 20:03:28 +00:00 |
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Evan Cheng
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1e4f55200d
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Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions.
llvm-svn: 103994
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2010-05-17 23:24:12 +00:00 |
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Evan Cheng
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f2c9a96f3c
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Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def.
llvm-svn: 103984
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2010-05-17 22:09:49 +00:00 |
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Evan Cheng
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29c463862e
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Careful with reg_sequence coalescing to not to overwrite sub-register indices.
llvm-svn: 103971
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2010-05-17 20:57:12 +00:00 |
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Evan Cheng
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3d98b996ff
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Turn on -neon-reg-sequence by default.
Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!
llvm-svn: 103960
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2010-05-17 19:51:20 +00:00 |
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