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1604 Commits

Author SHA1 Message Date
Anton Korobeynikov
fb80151c42 Removed tabs everywhere except autogenerated & external files. Add make 
target for tabs checking.

llvm-svn: 36146
 2007-04-16 18:10:23 +00:00
Chris Lattner
6bd7b7b30b disable switch lowering using shift/and. It still breaks ppc bootstrap for 
some reason.  :(  Will investigate.

llvm-svn: 36011
 2007-04-14 19:39:41 +00:00
Anton Korobeynikov
8a1a84f96e Fix PR1325: Case range optimization was performed in the case it 
shouldn't. Also fix some "latent" bug on 64-bit platforms

llvm-svn: 35990
 2007-04-14 13:25:55 +00:00
Chris Lattner
7196f09edc disable shift/and lowering to work around PR1325 for now. 
llvm-svn: 35985
 2007-04-14 02:26:56 +00:00
Anton Korobeynikov
e288040abf Fix PR1323 : we haven't updated phi nodes in good manner :) 
llvm-svn: 35963
 2007-04-13 06:53:51 +00:00
Chris Lattner
5111499136 the result of an inline asm copy can be an arbitrary VT that the register 
class supports.  In the case of vectors, this means we often get the wrong
type (e.g. we get v4f32 instead of v8i16).  Make sure to convert the vector
result to the right type.  This fixes CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll

llvm-svn: 35944
 2007-04-12 06:00:20 +00:00
Chris Lattner
a77cb3ce68 fold noop vbitconvert instructions 
llvm-svn: 35943
 2007-04-12 05:58:43 +00:00
Chris Lattner
784a68a702 Fix weirdness handling single element vectors. 
llvm-svn: 35941
 2007-04-12 04:44:28 +00:00
Reid Spencer
c6251a7dfd For PR1284: 
Implement the "part_set" intrinsic.

llvm-svn: 35938
 2007-04-12 02:48:46 +00:00
Chris Lattner
18e4ac4107 fix an infinite loop compiling ldecod, notice by JeffC. 
llvm-svn: 35910
 2007-04-11 16:51:53 +00:00
Chris Lattner
a083ffcad7 Fix this harder. 
llvm-svn: 35888
 2007-04-11 06:50:51 +00:00
Chris Lattner
c5f85d3738 don't create shifts by zero, fix some problems with my previous patch 
llvm-svn: 35887
 2007-04-11 06:43:25 +00:00
Chris Lattner
65786b078c Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which often 
allows other simplifications.  For example, this compiles:
int isnegative(unsigned int X) {
   return !(X < 2147483648U);
}

Into this code:

x86:
        movl 4(%esp), %eax
        shrl $31, %eax
        ret
arm:
        mov r0, r0, lsr #31
        bx lr
thumb:
        lsr r0, r0, #31
        bx lr

instead of:

x86:
        cmpl $0, 4(%esp)
        sets %al
        movzbl %al, %eax
        ret

arm:
        mov r3, #0
        cmp r0, #0
        movlt r3, #1
        mov r0, r3
        bx lr

thumb:
        mov r2, #1
        mov r1, #0
        cmp r0, #0
        blt LBB1_2      @entry
LBB1_1: @entry
        cpy r2, r1
LBB1_2: @entry
        cpy r0, r2
        bx lr

Testcase here: test/CodeGen/Generic/ispositive.ll

llvm-svn: 35883
 2007-04-11 05:32:27 +00:00
Chris Lattner
41189c63cc Codegen integer abs more efficiently using the trick from the PPC CWG. This 
improves codegen on many architectures.  Tests committed as CodeGen/*/iabs.ll

X86 Old:			X86 New:
_test:				_test:
   movl 4(%esp), %ecx		   movl 4(%esp), %eax
   movl %ecx, %eax		   movl %eax, %ecx
   negl %eax			   sarl $31, %ecx
   testl %ecx, %ecx		   addl %ecx, %eax
   cmovns %ecx, %eax		   xorl %ecx, %eax
   ret				   ret

PPC Old:			PPC New:
_test:				_test:
   cmpwi cr0, r3, -1		   srawi r2, r3, 31
   neg r2, r3			   add r3, r3, r2
   bgt cr0, LBB1_2 ;		   xor r3, r3, r2
LBB1_1: ;			   blr
   mr r3, r2
LBB1_2: ;
   blr

ARM Old:			ARM New:
_test:				_test:
   rsb r3, r0, #0		   add r3, r0, r0, asr #31
   cmp r0, #0			   eor r0, r3, r0, asr #31
   movge r3, r0			   bx lr
   mov r0, r3
   bx lr

Thumb Old:			Thumb New:
_test:				_test:
   neg r2, r0			   asr r2, r0, #31
   cmp r0, #0			   add r0, r0, r2
   bge LBB1_2			   eor r0, r2
LBB1_1: @			   bx lr
   cpy r0, r2
LBB1_2: @
   bx lr


Sparc Old:			Sparc New:
test:				test:
   save -96, %o6, %o6		   save -96, %o6, %o6
   sethi 0, %l0			   sra %i0, 31, %l0
   sub %l0, %i0, %l0		   add %i0, %l0, %l1
   subcc %i0, -1, %l1		   xor %l1, %l0, %i0
   bg .BB1_2			   restore %g0, %g0, %g0
   nop				   retl
.BB1_1:				   nop
   or %g0, %l0, %i0
.BB1_2:
   restore %g0, %g0, %g0
   retl
   nop

It also helps alpha/ia64 :)

llvm-svn: 35881
 2007-04-11 05:11:38 +00:00
Reid Spencer
a472f66dd0 For PR1146: 
Put the parameter attributes in their own ParamAttr name space. Adjust the
rest of llvm as a result.

llvm-svn: 35877
 2007-04-11 02:44:20 +00:00
Chris Lattner
f269d84ca0 apparently some people commit without building the tree, or they forget to 
commit a LOT of files.

llvm-svn: 35858
 2007-04-10 03:20:39 +00:00
Jeff Cohen
e0bbbd3774 No longer needed. 
llvm-svn: 35850
 2007-04-09 23:42:32 +00:00
Chris Lattner
35f0417ec1 remove dead target hooks. 
llvm-svn: 35847
 2007-04-09 23:34:08 +00:00
Chris Lattner
39f65335d5 remove some dead target hooks, subsumed by isLegalAddressingMode 
llvm-svn: 35840
 2007-04-09 22:27:04 +00:00
Anton Korobeynikov
da964a2852 Use integer log for metric calculation 
llvm-svn: 35834
 2007-04-09 21:57:03 +00:00
Jeff Cohen
0475f3b4e9 Unbreak VC++ build. 
llvm-svn: 35817
 2007-04-09 14:32:59 +00:00
Anton Korobeynikov
506eaf7915 Next stage into switch lowering refactoring 
1. Fix some bugs in the jump table lowering threshold
2. Implement much better metric for optimal pivot selection
3. Tune thresholds for different lowering methods
4. Implement shift-and trick for lowering small (<machine word
length) cases with few destinations. Good testcase will follow.

llvm-svn: 35816
 2007-04-09 12:31:58 +00:00
Reid Spencer
71b79e3d99 For PR1146: 
Adapt handling of parameter attributes to use the new ParamAttrsList class.

llvm-svn: 35814
 2007-04-09 06:17:21 +00:00
Chris Lattner
7b2decfa0a implement CodeGen/X86/inline-asm-x-scalar.ll:test3 
llvm-svn: 35802
 2007-04-09 05:31:20 +00:00
Chris Lattner
18d6718e78 add some assertions 
llvm-svn: 35800
 2007-04-09 05:23:13 +00:00
Chris Lattner
b49917da92 Fix PR1316 
llvm-svn: 35783
 2007-04-09 00:33:58 +00:00
Chris Lattner
e55ecfb870 Fix for CodeGen/X86/2007-04-08-InlineAsmCrash.ll and PR1314 
llvm-svn: 35779
 2007-04-08 22:23:26 +00:00
Chris Lattner
1c741e95d3 minor comment fix 
llvm-svn: 35696
 2007-04-06 17:47:14 +00:00
Reid Spencer
85460acfbf Change the bit_part_select (non)implementation from "return 0" to abort. 
llvm-svn: 35679
 2007-04-05 01:20:18 +00:00
Reid Spencer
cce90f55ed Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic. 
llvm-svn: 35678
 2007-04-04 23:48:25 +00:00
Anton Korobeynikov
915e61736b Properly emit range comparisons for switch cases, where neighbour cases 
go to the same destination. Now we're producing really good code for
switch-lower-feature.ll testcase

llvm-svn: 35672
 2007-04-04 21:14:49 +00:00
Scott Michel
16627a542f 1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL. 
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.

llvm-svn: 35605
 2007-04-02 21:36:32 +00:00
Reid Spencer
3a0843e734 For PR1297: 
Adjust for changes in the bit counting intrinsics. They all return i32
now so we have to trunc/zext the DAG node accordingly.

llvm-svn: 35546
 2007-04-01 07:34:11 +00:00
Reid Spencer
a090ffb2ab For PR1297: 
Change getOperationName to return std::string instead of const char*

llvm-svn: 35545
 2007-04-01 07:32:19 +00:00
Chris Lattner
f6a6d3c8b0 move a bunch of code out of the sdisel pass into its own opt pass "codegenprepare". 
llvm-svn: 35529
 2007-03-31 04:18:03 +00:00
Chris Lattner
f2d71d49e2 switch TL::getValueType to use MVT::getValueType. 
llvm-svn: 35527
 2007-03-31 04:05:24 +00:00
Chris Lattner
ac3f81508c add one addressing mode description hook to rule them all. 
llvm-svn: 35520
 2007-03-30 23:14:50 +00:00
Dale Johannesen
4bbd2eefba Fix incorrect combination of different loads. Reenable zext-over-truncate 
combination.

llvm-svn: 35517
 2007-03-30 21:38:07 +00:00
Evan Cheng
ccee35fd0d Disable load width reduction xform of variant (zext (truncate load x)) for 
big endian targets until llvm-gcc build issue has been resolved.

llvm-svn: 35449
 2007-03-29 07:56:46 +00:00
Evan Cheng
4388043b25 Scale 1 is always ok. 
llvm-svn: 35407
 2007-03-28 01:55:52 +00:00
Evan Cheng
c2cba18f2b Remove isLegalAddressImmediate. 
llvm-svn: 35406
 2007-03-28 01:53:55 +00:00
Evan Cheng
07c42d43a2 GEP index sinking fixes: 
1) Take address scale into consideration. e.g. i32* -> scale 4.
2) Examine all the users of GEP.
3) Generalize to inter-block GEP's (no longer uses loopinfo).
4) Don't do xform if GEP has other variable index(es).

llvm-svn: 35403
 2007-03-28 01:49:39 +00:00
Anton Korobeynikov
37a0bfe128 Remove dead code 
llvm-svn: 35380
 2007-03-27 12:05:48 +00:00
Anton Korobeynikov
3a9d68181a Split big monster into small helpers. No functionality change. 
llvm-svn: 35379
 2007-03-27 11:29:11 +00:00
Evan Cheng
c42406b5ad SDISel does not preserve all, it changes CFG and other info. 
llvm-svn: 35376
 2007-03-27 00:53:36 +00:00
Evan Cheng
8275f0e0af SIGN_EXTEND_INREG requires one extra operand, a ValueType node. 
llvm-svn: 35350
 2007-03-26 07:12:51 +00:00
Anton Korobeynikov
7037826c86 First step of switch lowering refactoring: perform worklist-driven 
strategy, emit JT's where possible.

llvm-svn: 35338
 2007-03-25 15:07:15 +00:00
Chris Lattner
77f0479833 Implement support for vector operands to inline asm, implementing 
CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll

llvm-svn: 35332
 2007-03-25 05:00:54 +00:00
Chris Lattner
3d7efa2586 implement initial support for the silly X constraint. Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll 
llvm-svn: 35327
 2007-03-25 04:35:41 +00:00
Chris Lattner
843e44503c Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll 
llvm-svn: 35324
 2007-03-25 02:18:14 +00:00