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3543 Commits

Author SHA1 Message Date
Nate Begeman
866b4b4d45 Fix the updating of the machine CFG when a PHI node was in a successor of 
the jump table's range check block.  This re-enables 100% dense jump tables
by default on PPC & x86

llvm-svn: 27952
 2006-04-23 06:26:20 +00:00
Nate Begeman
3e04bb482b Code cleanup associated with jump tables, thanks to Chris for noticing 
these.

llvm-svn: 27950
 2006-04-22 23:52:35 +00:00
Nate Begeman
ecb1dafd3d Turn of jump tables for a bit, there are still some issues to work out with 
updating the machine CFG.

llvm-svn: 27949
 2006-04-22 23:51:56 +00:00
Nate Begeman
4ca2ea5b43 JumpTable support! What this represents is working asm and jit support for 
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947
 2006-04-22 18:53:45 +00:00
Chris Lattner
b21d3bfd1f The BFS scheduler is apparently nondeterminstic (causes many llvmgcc bootstrap 
miscompares).  Switch RISC targets to use the list-td scheduler, which isn't.

llvm-svn: 27933
 2006-04-21 17:16:16 +00:00
Chris Lattner
662e940f73 Fix a couple more memory issues 
llvm-svn: 27930
 2006-04-21 15:32:26 +00:00
Chris Lattner
cc47ab3305 Fix a really subtle and obnoxious memory bug that caused issues with an 
llvm-gcc4 boostrap.  Whenever a node is deleted by the dag combiner, it
*must* be returned by the visit function, or the dag combiner will not
know that the node has been processed (and will, e.g., send it to the
target dag combine xforms).

llvm-svn: 27922
 2006-04-20 23:55:59 +00:00
Chris Lattner
dcc1f995eb This field no longer exists 
llvm-svn: 27899
 2006-04-20 18:32:41 +00:00
Chris Lattner
a38c3580bd Remove some of the obvious V9-specific cruft 
llvm-svn: 27893
 2006-04-20 18:08:53 +00:00
Evan Cheng
a320abc494 Turn a VAND into a VECTOR_SHUFFLE is applicable. 
DAG combiner can turn a VAND V, <-1, 0, -1, -1>, i.e. vector clear elements,
into a vector shuffle with a zero vector. It only does so when TLI tells it
the xform is profitable.

llvm-svn: 27874
 2006-04-20 08:56:16 +00:00
Chris Lattner
bc1b262725 Implement folding of a bunch of binops with undef 
llvm-svn: 27863
 2006-04-20 05:39:12 +00:00
Chris Lattner
73eb58e1a2 Simplify some code 
llvm-svn: 27846
 2006-04-19 23:17:50 +00:00
Chris Lattner
916ae0775e Fix handling of calls in functions that use vectors. This fixes a crash on 
the code in GCC PR26546.

llvm-svn: 27780
 2006-04-17 22:10:08 +00:00
Chris Lattner
bec79b4a59 Add a MachineInstr::eraseFromParent convenience method. 
llvm-svn: 27775
 2006-04-17 21:35:41 +00:00
Chris Lattner
326870b40b Codegen insertelement with constant insertion points as scalar_to_vector 
and a shuffle.  For this:

void %test2(<4 x float>* %F, float %f) {
        %tmp = load <4 x float>* %F             ; <<4 x float>> [#uses=2]
        %tmp3 = add <4 x float> %tmp, %tmp              ; <<4 x float>> [#uses=1]
        %tmp2 = insertelement <4 x float> %tmp3, float %f, uint 2               ; <<4 x float>> [#uses=2]
        %tmp6 = add <4 x float> %tmp2, %tmp2            ; <<4 x float>> [#uses=1]
        store <4 x float> %tmp6, <4 x float>* %F
        ret void
}

we now get this on X86 (which will get better):

_test2:
        movl 4(%esp), %eax
        movaps (%eax), %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, %xmm1
        shufps $3, %xmm1, %xmm1
        movaps %xmm0, %xmm2
        shufps $1, %xmm2, %xmm2
        unpcklps %xmm1, %xmm2
        movss 8(%esp), %xmm1
        unpcklps %xmm1, %xmm0
        unpcklps %xmm2, %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, (%eax)
        ret

instead of:

_test2:
        subl $28, %esp
        movl 32(%esp), %eax
        movaps (%eax), %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, (%esp)
        movss 36(%esp), %xmm0
        movss %xmm0, 8(%esp)
        movaps (%esp), %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, (%eax)
        addl $28, %esp
        ret

llvm-svn: 27765
 2006-04-17 19:21:01 +00:00
Chris Lattner
91226e5799 Add support for promoting stores from one legal type to another, allowing us 
to write one pattern for vector stores instead of 4.

llvm-svn: 27730
 2006-04-16 01:36:45 +00:00
Chris Lattner
7e7ad593cc Make these predicates return true for bit_convert(buildvector)'s as well as 
buildvectors.

llvm-svn: 27723
 2006-04-15 23:38:00 +00:00
Chris Lattner
086e986e94 Make this assertion better 
llvm-svn: 27695
 2006-04-14 06:08:35 +00:00
Reid Spencer
709eaacb36 Expand some code with temporary variables to rid ourselves of the warning 
about "dereferencing type-punned pointer will break strict-aliasing rules"

llvm-svn: 27671
 2006-04-13 18:29:58 +00:00
Evan Cheng
119266ea92 Promote vector AND, OR, and XOR 
llvm-svn: 27632
 2006-04-12 21:20:24 +00:00
Evan Cheng
be8a8933e6 Vector type promotion for ISD::LOAD and ISD::SELECT 
llvm-svn: 27606
 2006-04-12 16:33:18 +00:00
Chris Lattner
d3b504ae10 Implement support for the formal_arguments node. To get this, targets shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload 
llvm-svn: 27604
 2006-04-12 16:20:43 +00:00
Chris Lattner
417b96b6dd Don't memoize vloads in the load map! Don't memoize them anywhere here, let 
getNode do it.  This fixes CodeGen/Generic/2006-04-11-vecload.ll

llvm-svn: 27602
 2006-04-12 03:25:41 +00:00
Evan Cheng
7256b0ae05 Only get Tmp2 for cases where number of operands is > 1. Fixed return void. 
llvm-svn: 27586
 2006-04-11 06:33:39 +00:00
Chris Lattner
6cf3bbbe17 add some todos 
llvm-svn: 27580
 2006-04-11 02:00:08 +00:00
Chris Lattner
2eb22eef7d Add basic support for legalizing returns of vectors 
llvm-svn: 27578
 2006-04-11 01:31:51 +00:00
Jim Laskey
dca2655daa Use existing information. 
llvm-svn: 27574
 2006-04-10 23:09:19 +00:00
Evan Cheng
cb73b8d419 Missing break 
llvm-svn: 27559
 2006-04-10 18:54:36 +00:00
Chris Lattner
02274a5265 Add code generator support for VSELECT 
llvm-svn: 27542
 2006-04-08 22:22:57 +00:00
Chris Lattner
e1401e3610 Canonicalize vvector_shuffle(x,x) -> vvector_shuffle(x,undef) to enable patterns 
to match again :)

llvm-svn: 27533
 2006-04-08 05:34:25 +00:00
Chris Lattner
098c01e94e Codegen shufflevector as VVECTOR_SHUFFLE 
llvm-svn: 27529
 2006-04-08 04:15:24 +00:00
Chris Lattner
101ea66813 add a sanity check: LegalizeOp should return a value that is the same type 
as its input.

llvm-svn: 27528
 2006-04-08 04:13:17 +00:00
Evan Cheng
78e3d565af INSERT_VECTOR_ELT lowering bug: 
store vector to $esp
  store element to $esp + sizeof(VT) * index
  load  vector from $esp
The bug is VT is the type of the vector element, not the type of the vector!

llvm-svn: 27517
 2006-04-08 01:46:37 +00:00
Chris Lattner
aa3185f12e Stub out shufflevector 
llvm-svn: 27514
 2006-04-08 01:19:25 +00:00
Jim Laskey
7d4592733c Remove section change in function end, preventing override of function's real 
section.

llvm-svn: 27503
 2006-04-08 00:35:59 +00:00
Jim Laskey
c0d6518f27 Make sure that debug labels are defined within the same section and after the 
entry point of a function.

llvm-svn: 27494
 2006-04-07 20:44:42 +00:00
Jim Laskey
2d7298c362 Foundation for call frame information. 
llvm-svn: 27491
 2006-04-07 16:34:46 +00:00
Evan Cheng
613996c55e 1. If both vector operands of a vector_shuffle are undef, turn it into an undef. 
2. A shuffle mask element can also be an undef.

llvm-svn: 27472
 2006-04-06 23:20:43 +00:00
Chris Lattner
4a2413a590 Make a vector live across blocks have the correct Vec type. This fixes 
CodeGen/X86/2006-04-04-CrossBlockCrash.ll

llvm-svn: 27436
 2006-04-05 06:54:42 +00:00
Evan Cheng
9fa8959dce Exapnd a VECTOR_SHUFFLE to a BUILD_VECTOR if target asks for it to be expanded 
or custom lowering fails.

llvm-svn: 27432
 2006-04-05 06:07:11 +00:00
Chris Lattner
4ea52cac01 Do not create ZEXTLOAD's unless we are before legalize or the operation is 
legal.

llvm-svn: 27402
 2006-04-04 17:39:18 +00:00
Chris Lattner
6be79823e7 * Add supprot for SCALAR_TO_VECTOR operations where the input needs to be 
promoted/expanded (e.g. SCALAR_TO_VECTOR from i8/i16 on PPC).
* Add support for targets to request that VECTOR_SHUFFLE nodes be promoted
  to a canonical type, for example, we only want v16i8 shuffles on PPC.
* Move isShuffleLegal out of TLI into Legalize.
* Teach isShuffleLegal to allow shuffles that need to be promoted.

llvm-svn: 27399
 2006-04-04 17:23:26 +00:00
Chris Lattner
a9e77d14c7 Constant fold bitconvert(undef) 
llvm-svn: 27391
 2006-04-04 01:02:22 +00:00
Chris Lattner
b710a81e54 The stack alignment is now computed dynamically, just verify it is correct. 
llvm-svn: 27380
 2006-04-03 21:39:57 +00:00
Chris Lattner
6bc4b9c7f8 Remove unused method 
llvm-svn: 27379
 2006-04-03 21:39:03 +00:00
Chris Lattner
e1e3adf802 Add a missing check, this fixes UnitTests/Vector/sumarray.c 
llvm-svn: 27375
 2006-04-03 17:29:28 +00:00
Chris Lattner
04c00fc844 Add a missing check, which broke a bunch of vector tests. 
llvm-svn: 27374
 2006-04-03 17:21:50 +00:00
Andrew Lenharth
94f012f606 back this out 
llvm-svn: 27367
 2006-04-03 03:16:50 +00:00
Andrew Lenharth
015eaf5f33 This should be a win of every arch 
llvm-svn: 27364
 2006-04-02 21:42:45 +00:00
Chris Lattner
4993249a04 Add a little dag combine to compile this: 
int %AreSecondAndThirdElementsBothNegative(<4 x float>* %in) {
entry:
        %tmp1 = load <4 x float>* %in           ; <<4 x float>> [#uses=1]
        %tmp = tail call int %llvm.ppc.altivec.vcmpgefp.p( int 1, <4 x float> < float 0x7FF8000000000000, float 0.000000e+00, float 0.000000e+00, float 0x7FF8000000000000 >, <4 x float> %tmp1 )           ; <int> [#uses=1]
        %tmp = seteq int %tmp, 0                ; <bool> [#uses=1]
        %tmp3 = cast bool %tmp to int           ; <int> [#uses=1]
        ret int %tmp3
}

into this:

_AreSecondAndThirdElementsBothNegative:
        mfspr r2, 256
        oris r4, r2, 49152
        mtspr 256, r4
        li r4, lo16(LCPI1_0)
        lis r5, ha16(LCPI1_0)
        lvx v0, 0, r3
        lvx v1, r5, r4
        vcmpgefp. v0, v1, v0
        mfcr r3, 2
        rlwinm r3, r3, 27, 31, 31
        mtspr 256, r2
        blr

instead of this:

_AreSecondAndThirdElementsBothNegative:
        mfspr r2, 256
        oris r4, r2, 49152
        mtspr 256, r4
        li r4, lo16(LCPI1_0)
        lis r5, ha16(LCPI1_0)
        lvx v0, 0, r3
        lvx v1, r5, r4
        vcmpgefp. v0, v1, v0
        mfcr r3, 2
        rlwinm r3, r3, 27, 31, 31
        xori r3, r3, 1
        cntlzw r3, r3
        srwi r3, r3, 5
        mtspr 256, r2
        blr

llvm-svn: 27356
 2006-04-02 06:11:11 +00:00