Commit Graph

3543 Commits

Author SHA1 Message Date
Chris Lattner
1408c05a8b The 81st column doesn't like code in it.
llvm-svn: 24943
2005-12-22 05:23:45 +00:00
Reid Spencer
2335fc2f44 Add an eol at the end to shut gcc sup.
llvm-svn: 24926
2005-12-22 01:41:00 +00:00
Evan Cheng
9cdc16c6d3 * Fix a GlobalAddress lowering bug.
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.

llvm-svn: 24921
2005-12-21 23:05:39 +00:00
Jim Laskey
9e296bee9a Disengage DEBUG_LOC from non-PPC targets.
llvm-svn: 24919
2005-12-21 20:51:37 +00:00
Evan Cheng
c1583dbd63 * Added support for X86 RET with an additional operand to specify number of
bytes to pop off stack.
* Added support for X86 SETCC.

llvm-svn: 24917
2005-12-21 20:21:51 +00:00
Jim Laskey
7b52a923b8 Start of Dwarf framework.
llvm-svn: 24914
2005-12-21 19:48:16 +00:00
Chris Lattner
0fab459362 make sure to relegalize all cases
llvm-svn: 24911
2005-12-21 19:40:42 +00:00
Chris Lattner
44c07ed61a enable the gep isel opt
llvm-svn: 24910
2005-12-21 19:36:36 +00:00
Chris Lattner
ac12f68424 fix a bug I introduced that broke recursive expansion of nodes (e.g. scalarizing vectors)
llvm-svn: 24905
2005-12-21 18:02:52 +00:00
Chris Lattner
803a575616 Lower ConstantAggregateZero into zeros
llvm-svn: 24890
2005-12-21 02:43:26 +00:00
Chris Lattner
434ffe49a9 Don't emit a null terminator, nor anything after it, to the ctor/dtor list
llvm-svn: 24887
2005-12-21 01:17:37 +00:00
Evan Cheng
6af02635a7 Added a hook to print out names of target specific DAG nodes.
llvm-svn: 24877
2005-12-20 06:22:03 +00:00
Chris Lattner
2af3ee4bdd Fix a nasty latent bug in the legalizer that was triggered by my patch
last night, breaking crafty and twolf.  Make sure that the newly found
legal nodes are themselves not re-legalized until the next iteration.

Also, since this functionality exists now, we can reduce number of legalizer
iterations by depending on this behavior instead of having to misuse 'do
another iteration' to get the same effect.

llvm-svn: 24875
2005-12-20 00:53:54 +00:00
Evan Cheng
6fc31046aa X86 conditional branch support.
llvm-svn: 24870
2005-12-19 23:12:38 +00:00
Evan Cheng
9fd9541367 Print out opcode number if it's an unknown target node.
llvm-svn: 24869
2005-12-19 23:11:49 +00:00
Chris Lattner
50b2d302d5 Fix a case where the DAG Combiner would accidentally CSE flag-producing nodes,
creating graphs that cannot be scheduled.

llvm-svn: 24866
2005-12-19 22:21:21 +00:00
Jim Laskey
9b9688aeb8 Amend comment.
llvm-svn: 24861
2005-12-19 16:32:26 +00:00
Jim Laskey
ce23987e6b Create a strong dependency for loads following stores. This will leave a
latency period between the two.

llvm-svn: 24860
2005-12-19 16:30:13 +00:00
Chris Lattner
c06da626b4 Make sure to relegalize new nodes
llvm-svn: 24843
2005-12-18 23:54:29 +00:00
Jeff Cohen
c7cb351aac Keep VC++ happy.
llvm-svn: 24835
2005-12-18 22:20:05 +00:00
Chris Lattner
ebcfa0c210 More corrections for flagged copyto/from reg
llvm-svn: 24828
2005-12-18 15:36:21 +00:00
Chris Lattner
e3c67e97c7 legalize copytoreg and copyfromreg nodes that have flag operands correctly.
llvm-svn: 24826
2005-12-18 15:27:43 +00:00
Jim Laskey
c97b7d0be9 Fix a bug Sabre was having where the DAG root was a group. The group dominator
needed to be added to the ordering list, not the first member of the group.

llvm-svn: 24816
2005-12-18 04:40:52 +00:00
Jim Laskey
e220821deb Groups were not emitted if the dominator node and the node in the ordering list
were not the same node.  Ultimately the test was bogus.

llvm-svn: 24815
2005-12-18 03:59:21 +00:00
Chris Lattner
cf12118965 Simplify code
llvm-svn: 24806
2005-12-18 01:03:46 +00:00
Chris Lattner
bf0bd99e03 allow custom expansion of BR_CC
llvm-svn: 24804
2005-12-17 23:46:46 +00:00
Evan Cheng
225a4d0d6d X86 lowers SELECT to a cmp / test followed by a conditional move.
llvm-svn: 24754
2005-12-17 01:21:05 +00:00
Jim Laskey
7c462768ed Added source file/line correspondence for dwarf (PowerPC only at this point.)
llvm-svn: 24748
2005-12-16 22:45:29 +00:00
Chris Lattner
83e4407379 Don't create SEXTLOAD/ZEXTLOAD instructions that the target doesn't support
if after legalize.  This fixes IA64 failures.

llvm-svn: 24725
2005-12-15 19:02:38 +00:00
Chris Lattner
d39c60fcc8 When folding loads into ops, immediately replace uses of the op with the
load.  This reduces number of worklist iterations and avoid missing optimizations
depending on folding of things into sext_inreg nodes (which aren't supported by
all targets).
Tested by Regression/CodeGen/X86/extend.ll:test2

llvm-svn: 24712
2005-12-14 19:25:30 +00:00
Chris Lattner
7dac1083da Fix the (zext (zextload)) case to trigger, similarly for sign extends.
Allow (zext (truncate)) to apply after legalize if the target supports
AND (which all do).

This compiles
short %foo() {
        %tmp.0 = load ubyte* %X         ; <ubyte> [#uses=1]
        %tmp.3 = cast ubyte %tmp.0 to short             ; <short> [#uses=1]
        ret short %tmp.3
}

to:
_foo:
        movzbl _X, %eax
        ret

instead of:

_foo:
        movzbl _X, %eax
        movzbl %al, %eax
        ret

thanks to Evan for pointing this out.

llvm-svn: 24709
2005-12-14 19:05:06 +00:00
Chris Lattner
f753d1a574 Fix a miscompilation in crafty due to a recent patch
llvm-svn: 24706
2005-12-14 07:58:38 +00:00
Evan Cheng
bce7c47306 Fold (zext (load x) to (zextload x).
llvm-svn: 24702
2005-12-14 02:19:23 +00:00
Chris Lattner
5d4e61dd87 Don't lump the filename and working dir together
llvm-svn: 24697
2005-12-13 17:40:33 +00:00
Chris Lattner
f0e9aef954 Add a couple more fields, move ctor init list to .cpp file, add support
for emitting the ctor/dtor list for common targets.

llvm-svn: 24694
2005-12-13 06:32:10 +00:00
Nate Begeman
956aef45c9 Lowering constant pool entries on ppc exposed a bug in the recently added
ConstantVec legalizing code, which would return constantpool nodes that
were not of the target's pointer type.

llvm-svn: 24691
2005-12-13 03:03:23 +00:00
Chris Lattner
9e8b633ec1 Accept and ignore prefetches for now
llvm-svn: 24678
2005-12-12 22:51:16 +00:00
Chris Lattner
b42ce7ca63 Fix CodeGen/Generic/2005-12-12-ExpandSextInreg.ll
llvm-svn: 24677
2005-12-12 22:27:43 +00:00
Chris Lattner
f1a54c0d14 Minor tweak to get isel opt
llvm-svn: 24663
2005-12-11 09:05:13 +00:00
Nate Begeman
4e56db674c Add support for TargetConstantPool nodes to the dag isel emitter, and use
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.

llvm-svn: 24657
2005-12-10 02:36:00 +00:00
Evan Cheng
dadc1057ac Added new getNode and getTargetNode variants for X86 stores.
llvm-svn: 24653
2005-12-10 00:37:58 +00:00
Chris Lattner
a6f835f5a0 Avoid emitting two tabs when switching to a named section
llvm-svn: 24646
2005-12-09 19:28:49 +00:00
Chris Lattner
268d457b69 Teach legalize how to promote sext_inreg to fix a problem Andrew pointed
out to me.

llvm-svn: 24644
2005-12-09 17:32:47 +00:00
Chris Lattner
be73d6eece improve code insertion in two ways:
1. Only forward subst offsets into loads and stores, not into arbitrary
   things, where it will likely become a load.
2. If the source is a cast from pointer, forward subst the cast as well,
   allowing us to fold the cast away (improving cases when the cast is
   from an alloca or global).

This hasn't been fully tested, but does appear to further reduce register
pressure and improve code.  Lets let the testers grind on it a bit. :)

llvm-svn: 24640
2005-12-08 08:00:12 +00:00
Nate Begeman
ae89d862f5 Fix a crash where ConstantVec nodes were being generated with the wrong
type when the target did not support them.  Also teach Legalize how to
expand ConstantVecs.

This allows us to generate

_test:
        lwz r2, 12(r3)
        lwz r4, 8(r3)
        lwz r5, 4(r3)
        lwz r6, 0(r3)
        addi r2, r2, 4
        addi r4, r4, 3
        addi r5, r5, 2
        addi r6, r6, 1
        stw r2, 12(r3)
        stw r4, 8(r3)
        stw r5, 4(r3)
        stw r6, 0(r3)
        blr

For:

void %test(%v4i *%P) {
        %T = load %v4i* %P
        %S = add %v4i %T, <int 1, int 2, int 3, int 4>
        store %v4i %S, %v4i * %P
        ret void
}

On PowerPC.

llvm-svn: 24633
2005-12-07 19:48:11 +00:00
Chris Lattner
57c882edf8 Only transform (sext (truncate x)) -> (sextinreg x) if before legalize or
if the target supports the resultant sextinreg

llvm-svn: 24632
2005-12-07 18:02:05 +00:00
Chris Lattner
cbd3d01a43 Teach the dag combiner to turn a truncate/sign_extend pair into a sextinreg
when the types match up.  This allows the X86 backend to compile:

sbyte %toggle_value(sbyte* %tmp.1) {
        %tmp.2 = load sbyte* %tmp.1
        ret sbyte %tmp.2
}

to this:

_toggle_value:
        mov %EAX, DWORD PTR [%ESP + 4]
        movsx %EAX, BYTE PTR [%EAX]
        ret

instead of this:

_toggle_value:
        mov %EAX, DWORD PTR [%ESP + 4]
        movsx %EAX, BYTE PTR [%EAX]
        movsx %EAX, %AL
        ret

noticed in Shootout/objinst.

-Chris

llvm-svn: 24630
2005-12-07 07:11:03 +00:00
Nate Begeman
41b1cdc771 Teach the SelectionDAG ISel how to turn ConstantPacked values into
constant nodes with vector types.  Also teach the asm printer how to print
ConstantPacked constant pool entries.  This allows us to generate altivec
code such as the following, which adds a vector constantto a packed float.

LCPI1_0:  <4 x float> < float 0.0e+0, float 0.0e+0, float 0.0e+0, float 1.0e+0 >
        .space  4
        .space  4
        .space  4
        .long   1065353216      ; float 1
        .text
        .align  4
        .globl  _foo
_foo:
        lis r2, ha16(LCPI1_0)
        la r2, lo16(LCPI1_0)(r2)
        li r4, 0
        lvx v0, r4, r2
        lvx v1, r4, r3
        vaddfp v0, v1, v0
        stvx v0, r4, r3
        blr

For the llvm code:

void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = add <4 x float> %tmp1, < float 0.0, float 0.0, float 0.0, float 1.0 >
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}

llvm-svn: 24616
2005-12-06 06:18:55 +00:00
Chris Lattner
3539778883 Fix the #1 code quality problem that I have seen on X86 (and it also affects
PPC and other targets).  In a particular, consider code like this:

struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
   return a.x * b.x  +  a.y * b.y  +  a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
   Vector3 r;
   r.x = dot( a, b.a );
   r.y = dot( a, b.b );
   r.z = dot( a, b.c );
   return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
   for (int i = 0; i < n; i++)
      x[i] = mul( x[i], m );
}

we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them).  Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:

LBB3_1: ; no_exit.preheader
        li r2, 0
        addi r6, r3, 64        ;; 9 values live across the loop body!
        addi r7, r3, 56
        addi r8, r3, 48
        addi r9, r3, 40
        addi r10, r3, 32
        addi r11, r3, 24
        addi r12, r3, 16
        addi r30, r3, 8
LBB3_2: ; no_exit
        lfd f0, 0(r30)
        lfd f1, 8(r4)
        fmul f0, f1, f0
        lfd f2, 0(r3)        ;; no constant indices folded into the loads!
        lfd f3, 0(r4)
        lfd f4, 0(r10)
        lfd f5, 0(r6)
        lfd f6, 0(r7)
        lfd f7, 0(r8)
        lfd f8, 0(r9)
        lfd f9, 0(r11)
        lfd f10, 0(r12)
        lfd f11, 16(r4)
        fmadd f0, f3, f2, f0
        fmul f2, f1, f4
        fmadd f0, f11, f10, f0
        fmadd f2, f3, f9, f2
        fmul f1, f1, f6
        stfd f0, 0(r4)
        fmadd f0, f11, f8, f2
        fmadd f1, f3, f7, f1
        stfd f0, 8(r4)
        fmadd f0, f11, f5, f1
        addi r29, r4, 24
        stfd f0, 16(r4)
        addi r2, r2, 1
        cmpw cr0, r2, r5
        or r4, r29, r29
        bne cr0, LBB3_2 ; no_exit

uh, yuck.  With this patch, we now sink the constant offsets into the loop, producing
this code:

LBB3_1: ; no_exit.preheader
        li r2, 0
LBB3_2: ; no_exit
        lfd f0, 8(r3)
        lfd f1, 8(r4)
        fmul f0, f1, f0
        lfd f2, 0(r3)
        lfd f3, 0(r4)
        lfd f4, 32(r3)       ;; much nicer.
        lfd f5, 64(r3)
        lfd f6, 56(r3)
        lfd f7, 48(r3)
        lfd f8, 40(r3)
        lfd f9, 24(r3)
        lfd f10, 16(r3)
        lfd f11, 16(r4)
        fmadd f0, f3, f2, f0
        fmul f2, f1, f4
        fmadd f0, f11, f10, f0
        fmadd f2, f3, f9, f2
        fmul f1, f1, f6
        stfd f0, 0(r4)
        fmadd f0, f11, f8, f2
        fmadd f1, f3, f7, f1
        stfd f0, 8(r4)
        fmadd f0, f11, f5, f1
        addi r6, r4, 24
        stfd f0, 16(r4)
        addi r2, r2, 1
        cmpw cr0, r2, r5
        or r4, r6, r6
        bne cr0, LBB3_2 ; no_exit

This is much nicer as it reduces register pressure in the loop a lot.  On X86,
this takes the function from having 9 spilled registers to 2.  This should help
some spec programs on X86 (gzip?)

This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.

llvm-svn: 24606
2005-12-05 07:10:48 +00:00
Chris Lattner
8782b782cd dbg.stoppoint returns a value, don't forget to init it
llvm-svn: 24583
2005-12-03 18:50:48 +00:00