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3543 Commits

Author SHA1 Message Date
Chris Lattner
5aa75e4ce5 Fix yet another memset issue. 
llvm-svn: 19986
 2005-02-02 03:44:41 +00:00
Chris Lattner
4487b2e5a6 Fix some bugs andrew noticed legalizing memset for alpha 
llvm-svn: 19969
 2005-02-01 18:38:28 +00:00
Chris Lattner
f6c93e36c7 Improve conformance with the Misha spelling benchmark suite 
llvm-svn: 19930
 2005-01-30 00:09:23 +00:00
Chris Lattner
e6074aa08b adjust to ilist changes. 
llvm-svn: 19924
 2005-01-29 18:41:25 +00:00
Chris Lattner
bc7497d5f5 Alpha doesn't have a native f32 extload instruction. 
llvm-svn: 19880
 2005-01-28 22:58:25 +00:00
Chris Lattner
bf8c1ad313 implement legalization of truncates whose results and sources need to be 
truncated, e.g. (truncate:i8 something:i16) on a 32 or 64-bit RISC.

llvm-svn: 19879
 2005-01-28 22:52:50 +00:00
Chris Lattner
a4cfafe31a Get alpha working with memset/memcpy/memmove 
llvm-svn: 19878
 2005-01-28 22:29:18 +00:00
Chris Lattner
eb6614d719 CopyFromReg produces two values. Make sure that we remember that both are 
legalized, and actually return the correct result when we legalize the chain first.

llvm-svn: 19866
 2005-01-28 06:27:38 +00:00
Chris Lattner
0dfd7d3a0d Silence optimized warnings. 
llvm-svn: 19797
 2005-01-23 23:19:44 +00:00
Chris Lattner
fb5614506e Simplify/speedup the PEI by not having to scan for uses of the callee saved 
registers.  This information is computed directly by the register allocator
now.

llvm-svn: 19795
 2005-01-23 23:13:12 +00:00
Chris Lattner
3d527f7b61 Update physregsused info. 
llvm-svn: 19793
 2005-01-23 22:55:45 +00:00
Chris Lattner
24f0f0e28f Update this pass to set PhysRegsUsed info in MachineFunction. 
llvm-svn: 19792
 2005-01-23 22:51:56 +00:00
Chris Lattner
ae09d93b35 Update these register allocators to set the PhysRegUsed info in MachineFunction. 
llvm-svn: 19791
 2005-01-23 22:45:13 +00:00
Chris Lattner
304053c6ec Add support for the PhysRegsUsed array. 
llvm-svn: 19789
 2005-01-23 22:13:58 +00:00
Chris Lattner
ef2de322c6 Speed this up a bit by making ModifiedRegs a vector<char> not vector<bool> 
llvm-svn: 19787
 2005-01-23 21:45:01 +00:00
Chris Lattner
4add7e356f Adjust to changes in SelectionDAG interfaces 
The first half of correct chain insertion for libcalls. This is not enough
to fix Fhourstones yet though.

llvm-svn: 19781
 2005-01-23 04:42:50 +00:00
Chris Lattner
90b7c13f3a Remove the 3 HACK HACK HACKs I put in before, fixing them properly with 
the new TLI that is available.

Implement support for handling out of range shifts.  This allows us to
compile this code (a 64-bit rotate):

unsigned long long f3(unsigned long long x) {
  return (x << 32) | (x >> (64-32));
}

into this:

f3:
        mov %EDX, DWORD PTR [%ESP + 4]
        mov %EAX, DWORD PTR [%ESP + 8]
        ret

GCC produces this:

$ gcc t.c -masm=intel -O3 -S -o - -fomit-frame-pointer
..
f3:
        push    %ebx
        mov     %ebx, DWORD PTR [%esp+12]
        mov     %ecx, DWORD PTR [%esp+8]
        mov     %eax, %ebx
        mov     %edx, %ecx
        pop     %ebx
        ret

The Simple ISEL produces (eww gross):

f3:
        sub %ESP, 4
        mov DWORD PTR [%ESP], %ESI
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %ECX, DWORD PTR [%ESP + 12]
        mov %EAX, 0
        mov %ESI, 0
        or %EAX, %ECX
        or %EDX, %ESI
        mov %ESI, DWORD PTR [%ESP]
        add %ESP, 4
        ret

llvm-svn: 19780
 2005-01-23 04:39:44 +00:00
Chris Lattner
ffcb0ae329 Adjust to changes in SelectionDAG interface. 
llvm-svn: 19779
 2005-01-23 04:36:26 +00:00
Chris Lattner
eccb73d57f Get this to work for 64-bit systems. 
llvm-svn: 19763
 2005-01-22 23:04:37 +00:00
Chris Lattner
52c97fbea9 Implicitly defined registers can clobber callee saved registers too! 
This fixes the return-address-not-being-saved problem in the Alpha backend.

llvm-svn: 19741
 2005-01-22 00:49:16 +00:00
Chris Lattner
3bc78b2e0b More bugfixes for IA64 shifts. 
llvm-svn: 19739
 2005-01-22 00:33:03 +00:00
Chris Lattner
ec2183713c Fix problems with non-x86 targets. 
llvm-svn: 19738
 2005-01-22 00:31:52 +00:00
Chris Lattner
d637c96fac Add a nasty hack to fix Alpha/IA64 multiplies by a power of two. 
llvm-svn: 19737
 2005-01-22 00:20:42 +00:00
Chris Lattner
d53e763f18 Remove unneeded line. 
llvm-svn: 19736
 2005-01-21 23:43:12 +00:00
Chris Lattner
4f987bf16d test commit 
llvm-svn: 19735
 2005-01-21 23:38:56 +00:00
Chris Lattner
96e809c47d Unary token factor nodes are unneeded. 
llvm-svn: 19727
 2005-01-21 18:01:22 +00:00
Chris Lattner
aac464e6c0 Refactor libcall code a bit. Initial implementation of expanding int -> FP 
operations for 64-bit integers.

llvm-svn: 19724
 2005-01-21 06:05:23 +00:00
Chris Lattner
4d25c04f94 Simplify the shift-expansion code. 
llvm-svn: 19721
 2005-01-20 20:29:23 +00:00
Chris Lattner
b3f83b28a5 Expand add/sub into ADD_PARTS/SUB_PARTS instead of a non-existant libcall. 
llvm-svn: 19715
 2005-01-20 18:52:28 +00:00
Chris Lattner
1fe9b40981 implement add_parts/sub_parts. 
llvm-svn: 19714
 2005-01-20 18:50:55 +00:00
Chris Lattner
28d15860bd Add missing entry. 
llvm-svn: 19712
 2005-01-20 17:32:28 +00:00
Chris Lattner
96c26751ec Support targets that do not use i8 shift amounts. 
llvm-svn: 19707
 2005-01-19 22:31:21 +00:00
Chris Lattner
f840289291 Add an assertion that would have made more sense to duraid 
llvm-svn: 19704
 2005-01-19 21:32:07 +00:00
Chris Lattner
3d95c14d94 Add support for targets that pass args in registers to calls. 
llvm-svn: 19703
 2005-01-19 20:24:35 +00:00
Chris Lattner
55562fa99a Fold single use token factor nodes into other token factor nodes. 
llvm-svn: 19701
 2005-01-19 19:10:54 +00:00
Chris Lattner
0d03eb45a8 Realize the individual pieces of an expanded copytoreg/store/load are 
independent of each other.

llvm-svn: 19700
 2005-01-19 18:02:17 +00:00
Chris Lattner
9b75e148fd Know some identities about tokenfactor nodes. 
llvm-svn: 19699
 2005-01-19 18:01:40 +00:00
Chris Lattner
32a5f02598 Know some simple identities. This improves codegen for (1LL << N). 
llvm-svn: 19698
 2005-01-19 17:29:49 +00:00
Chris Lattner
1cffa73f2a Just in case, handle something that is both a use and a def. 
llvm-svn: 19696
 2005-01-19 17:11:51 +00:00
Chris Lattner
00c436824f When an instruction moves, make sure to update the VarInfo::Kills list as 
well as all of teh other stuff in livevar. This fixes the compiler crash
on fourinarow last night.

llvm-svn: 19695
 2005-01-19 17:09:15 +00:00
Chris Lattner
ea42c15da9 Use the TargetInstrInfo::commuteInstruction method to commute instructions 
instead of doing it manually.

llvm-svn: 19685
 2005-01-19 07:08:42 +00:00
Chris Lattner
2a7f8a94f4 Implement a way of expanding shifts. This applies to targets that offer 
select operations or to shifts that are by a constant.  This automatically
implements (with no special code) all of the special cases for shift by 32,
shift by < 32 and shift by > 32.

llvm-svn: 19679
 2005-01-19 04:19:40 +00:00
Chris Lattner
42993e45b6 Zero is cheaper than sign extend. 
llvm-svn: 19675
 2005-01-18 21:57:59 +00:00
Chris Lattner
d65c3f3118 Fix some fixmes (promoting bools for select and brcond), fix promotion 
of zero and sign extends.

llvm-svn: 19671
 2005-01-18 19:27:06 +00:00
Chris Lattner
a9d53f9fb9 Keep track of the retval type as well. 
llvm-svn: 19670
 2005-01-18 19:26:36 +00:00
Chris Lattner
9f2c4a5200 Teach legalize to promote copy(from|to)reg, instead of making the isel pass 
do it.  This results in better code on X86 for floats (because if strict
precision is not required, we can elide some more expensive double -> float
conversions like the old isel did), and allows other targets to emit
CopyFromRegs that are not legal for arguments.

llvm-svn: 19668
 2005-01-18 17:54:55 +00:00
Chris Lattner
2cb338d7b5 Teach legalize to promote SetCC results. 
llvm-svn: 19657
 2005-01-18 02:59:52 +00:00
Chris Lattner
b07e2d2084 Allow setcc operations to have nonbool types. 
llvm-svn: 19656
 2005-01-18 02:52:03 +00:00
Chris Lattner
2b4b79581d Fix the completely broken FP constant folds for setcc's. 
llvm-svn: 19651
 2005-01-18 02:11:55 +00:00
Chris Lattner
4d9651c760 Non-volatile loads can be freely reordered against each other. This fixes 
X86/reg-pressure.ll again, and allows us to do nice things in other cases.
For example, we now codegen this sort of thing:

int %loadload(int *%X, int* %Y) {
  %Z = load int* %Y
  %Y = load int* %X      ;; load between %Z and store
  %Q = add int %Z, 1
  store int %Q, int* %Y
  ret int %Y
}

Into this:

loadload:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EAX, DWORD PTR [%EAX]
        mov %ECX, DWORD PTR [%ESP + 8]
        inc DWORD PTR [%ECX]
        ret

where we weren't able to form the 'inc [mem]' before.  This also lets the
instruction selector emit loads in any order it wants to, which can be good
for register pressure as well.

llvm-svn: 19644
 2005-01-17 22:19:26 +00:00