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27 Commits

Author SHA1 Message Date
Matt Arsenault
a64ee177a0 Move declaration of variables down to first use. 
llvm-svn: 198794
 2014-01-08 21:47:14 +00:00
Matt Arsenault
eaa3a7efab Use llvm_unreachable instead of assert(0) 
llvm-svn: 196971
 2013-12-10 21:37:42 +00:00
Matt Arsenault
89cc49fe5d R600/SI: Add comments for number of used registers. 
llvm-svn: 196467
 2013-12-05 05:15:35 +00:00
Matt Arsenault
671a005e4a Indentation fixes 
llvm-svn: 194688
 2013-11-14 10:08:50 +00:00
Tom Stellard
6e1ee476ab R600/SI: Add compute support for CI v2 
v2:
  - Fix LDS size calculation

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 193621
 2013-10-29 16:37:28 +00:00
Tom Stellard
a66cafa096 R600/SI: Use S_LOAD_DWORD instructions for v8i32 and v16i32 
llvm-svn: 193212
 2013-10-23 00:44:12 +00:00
Matt Arsenault
65864e3182 R600/SI: Don't assert on SCC usage 
llvm-svn: 193198
 2013-10-22 21:11:31 +00:00
Tom Stellard
ed69925998 R600: Store disassembly in a special ELF section when feature +DumpCode is enabled. 
Patch by: Jay Cornwall

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 192523
 2013-10-12 05:02:51 +00:00
Michel Danzer
49812b5bbd R600/SI: Initial local memory support 
Enough for the radeonsi driver to use it for calculating derivatives.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186012
 2013-07-10 16:37:07 +00:00
Tom Stellard
c026e8bc8e R600: Add local memory support via LDS 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 185162
 2013-06-28 15:47:08 +00:00
Tom Stellard
a6c6e1bfc2 R600: Rework subtarget info and remove AMDILDevice classes 
This should simplify the subtarget definitions and make it easier to
add new ones.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183566
 2013-06-07 20:37:48 +00:00
Benjamin Kramer
d78bb468bd Move passes from namespace llvm into anonymous namespaces. Sort includes while there. 
llvm-svn: 182594
 2013-05-23 17:10:37 +00:00
Tom Stellard
043de4c5af R600: Emit config values in register / value pairs 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181228
 2013-05-06 17:50:51 +00:00
Vincent Lejeune
4a0beb5207 R600: config section now reports use of killgt 
llvm-svn: 180751
 2013-04-30 00:13:13 +00:00
Tom Stellard
34e4068d05 R600: Use SHT_PROGBITS for the .AMDGPU.config section 
The libelf implementation that is distributed here:
http://www.mr511.de/software/english.html
will not parse sections that are marked SHT_NULL.

llvm-svn: 180230
 2013-04-24 23:56:14 +00:00
Vincent Lejeune
117f075f6e R600: Use .AMDGPU.config section to emit stacksize 
llvm-svn: 180124
 2013-04-23 17:34:12 +00:00
Vincent Lejeune
98a7380859 R600: Emit used GPRs count 
llvm-svn: 179684
 2013-04-17 15:17:25 +00:00
Tom Stellard
cb97e3acfa R600/SI: Emit config values in register value pairs. 
Instead of emitting config values in a predefined order, the code
emitter will now emit a 32-bit register index followed by the 32-bit
config value.

llvm-svn: 179546
 2013-04-15 17:51:35 +00:00
Tom Stellard
3a7beafb32 R600/SI: Emit configuration value in the .AMDGPU.config ELF section 
llvm-svn: 179545
 2013-04-15 17:51:30 +00:00
Christian Konig
8b1ed28ef1 R600/SI: dynamical figure out the reg class of MIMG 
Depending on the number of bits set in the writemask.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179166
 2013-04-10 08:39:16 +00:00
Christian Konig
99ee0f4790 R600/SI: rework input interpolation v2 
v2: update CMakeLists.txt as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 176626
 2013-03-07 09:04:14 +00:00
Christian Konig
c756cb9901 R600/SI: cleanup literal handling v3 
Seems to be allot simpler, and also paves the
way for further improvements.

v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW,
    use VGPR0 in dummy EXP, avoid compiler warning, break
    after encoding the first literal.
v3: correctly use V_ADD_F32_e64

This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175354
 2013-02-16 11:28:22 +00:00
Tom Stellard
1c822a8929 R600/SI: cleanup VGPR encoding 
Remove all the unused code.

Patch by: Christian König

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174656
 2013-02-07 19:39:45 +00:00
Tom Stellard
538ceeb6e0 R600/SI: Add basic support for more integer vector types. 
v1i32, v2i32, v8i32 and v16i32.

Only add VGPR register classes for integer vector types, to avoid attempts
copying from VGPR to SGPR registers, which is not possible.

Patch By: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174632
 2013-02-07 17:02:09 +00:00
Tom Stellard
2e5e7a5bef R600: Emit function name in the AsmPrinter 
Emitting the function name allows us to check for it in the FileCheck
tests so we can make sure FileCheck is checking the output of the
correct function.

llvm-svn: 174392
 2013-02-05 17:09:11 +00:00
Chandler Carruth
be81023d74 Resort the #include lines in include/... and lib/... with the 
utils/sort_includes.py script.

Most of these are updating the new R600 target and fixing up a few
regressions that have creeped in since the last time I sorted the
includes.

llvm-svn: 171362
 2013-01-02 10:22:59 +00:00
Tom Stellard
75aadc2813 Add R600 backend 
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX

llvm-svn: 169915
 2012-12-11 21:25:42 +00:00