Commit Graph

2290 Commits

Author SHA1 Message Date
David Green
ac321cbb03 [AArch64][GlobalISel] Legalize Insert vector element (#81453)
This attempts to standardize and extend some of the insert vector
element lowering. Most notably:
- More types are handled by splitting illegal vectors.
- The index type for G_INSERT_VECTOR_ELT is canonicalized to
  TLI.getVectorIdxTy(), similar to extact_vector_element.
- Some of the existing patterns now have the index type specified to
  make sure they can apply to GISel too.
- The C++ selection code has been removed, relying on tablegen patterns.
- G_INSERT_VECTOR_ELT with small GPR input elements are pre-selected to
  use a i32 type, allowing the existing patterns to apply.
- Variable index inserts are lowered in post-legalizer lowering,
  expanding into a stack store and reload.
2024-04-08 08:44:13 +01:00
darkbuck
8e98435ae9 [GISel][Combine] Enhance combining on G_BUILD_VECTOR
Reviewers: aemerson, arsenm

Reviewed By: arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/87831
2024-04-06 18:33:01 -04:00
Amara Emerson
60fc4ac67a [GlobalISel] Don't form anyextending atomic loads.
Until we can reliably check the legality and improve our selection of these,
don't form them at all.
2024-04-05 13:34:59 -07:00
Michael Liao
a1b2f0cc44 Reland "[GlobalISel] Fix the infinite loop issue in commute_int_constant_to_rhs"
- That test needs to disable combine rules by name and hence requires `asserts`.
2024-04-05 10:34:12 -04:00
Gulfem Savrun Yeniceri
be8fd86f6a Revert "[GlobalISel] Fix the infinite loop issue in commute_int_constant_to_rhs"
This reverts commit 1f01c58044
because combine-commute-int-const-lhs.mir test failed in
multiple builders.
https://lab.llvm.org/buildbot/#/builders/124/builds/10375
https://luci-milo.appspot.com/ui/p/fuchsia/builders/prod/clang-linux-x64/b8751607530180046481/overview
2024-04-04 16:39:31 +00:00
Jay Foad
1b761205f2 [APInt] Add a simpler overload of multiplicativeInverse (#87610)
The current APInt::multiplicativeInverse takes a modulus which can be
any value, but all in-tree callers use a power of two. Moreover, most
callers want to use two to the power of the width of an existing APInt,
which is awkward because 2^N is not representable as an N-bit APInt.

Add a new overload of multiplicativeInverse which implicitly uses
2^BitWidth as the modulus.
2024-04-04 16:11:06 +01:00
darkbuck
1f01c58044 [GlobalISel] Fix the infinite loop issue in commute_int_constant_to_rhs
- When both operands are constant, the matcher runs into an infinite
  loop as the commutation should be applied only when LHS is a constant
  and RHS is not.

Reviewers: arsenm

Reviewed By: arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/87426
2024-04-03 20:52:21 -04:00
Michael Maitland
8aa3a77eaf [RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP for scalable vector types
This patch legalizes G_ZEXT, G_SEXT, and G_ANYEXT. If the type is a
legal mask type, then the instruction is legalized as the element-wise
select, where the condition on the select is the mask typed source
operand, and the true and false values are 1 or -1 (for
zero/any-extension and sign extension) and zero. If the type is a legal integer
or vector integer type, then the instruction is marked as legal.

The legalization of the extends may introduce a G_SPLAT_VECTOR, which
needs to be legalized in this patch for the extend test cases to pass.

A G_SPLAT_VECTOR is legal if the vector type is a legal integer or
floating point vector type and the source operand is sXLen type. This is
because the SelectionDAG patterns only support sXLen typed
ISD::SPLAT_VECTORS, and we'd like to reuse those patterns. A
G_SPLAT_VECTOR is cutom legalized if it has a legal s1 element vector
type and s1 scalar operand. It is legalized to G_VMSET_VL or G_VMCLR_VL
if the splat is all ones or all zeros respectivley. In the case of a
non-constant mask splat, we legalize by promoting the scalar value to
s8.

In order to get the s8 element vector back into s1 vector, we use a
G_ICMP. In order for the splat vector and extend tests to pass, we also
need to legalize G_ICMP in this patch.

A G_ICMP is legal if the destination type is a legal bool vector and the LHS and
RHS are legal integer vector types.
2024-04-03 15:27:15 -07:00
Thorsten Schütt
8bb9443333 [GlobalIsel] Combine G_EXTRACT_VECTOR_ELT (#85321)
preliminary steps
2024-04-02 09:01:24 +02:00
Vitaly Buka
20f56e1f8e [CodeGen] Add default lowering for llvm.allow.{runtime,ubsan}.check() (#86049)
RFC:
https://discourse.llvm.org/t/rfc-add-llvm-experimental-hot-intrinsic-or-llvm-hot/77641
2024-03-31 22:19:33 -07:00
Shilei Tian
3a106e5b2c [GlobalISel] Fold G_ICMP if possible (#86357)
This patch tries to fold `G_ICMP` if possible.
2024-03-29 15:59:50 -04:00
Shilei Tian
360f7f5674 [GlobalISel] Call setInstrAndDebugLoc before tryCombineAll (#86993)
This can remove all unnecessary redundant calls in each combiner.
2024-03-29 15:27:28 -04:00
Shilei Tian
661bb9daae [GlobalISel] Handle div-by-pow2 (#83155)
This patch adds similar handling of div-by-pow2 as in `SelectionDAG`.
2024-03-29 12:41:47 -04:00
Wang Pengcheng
610b9e23c5 [SDAG] Use shifts if ISD::MUL is illegal when lowering ISD::CTPOP (#86505)
We can avoid libcalls.

Fixes #86205
2024-03-29 15:38:39 +08:00
Shilei Tian
a8b90c047d [GlobalISel] Update MachineIRBuilder::buildAtomicRMW interface (#86851) 2024-03-27 17:41:30 -04:00
Michael Maitland
d345599c28 [GISEL][NFC] Use getElementCount instead of getNumElements in more places
These cases in particular are  done as a precommit to support
legalization, regbank selection, and instruction selection for extends,
splat vectors, and integer compares in #85938.
2024-03-26 17:41:46 -07:00
Michael Maitland
54a9f0e441 [RISCV][GISEL] Legalize, regbankselect, and instruction-select G_VSCALE (#85967)
G_VSCALE should be lowered using VLENB. If the type is not sXLen it
should be lowered using a G_VSCALE on the narrow type and a G_MUL.
regbank select and instruction select are straightforward so we really
only need to add tests to show it works.
2024-03-26 20:17:22 -04:00
Thorsten Schütt
da6cc4a24f [CodeGen] Add nneg and disjoint flags (#86650)
MachineInstr learned the new flags.
2024-03-26 18:44:34 +01:00
David Green
47f4a07a2f [GlobalISel] Add Knownbits for G_LOAD/ZEXTLOAD/SEXTLOAD with range metadata (#86431)
Similar to #80829 for GlobalISel.
2024-03-26 13:42:08 +00:00
David Green
fbc247367a [AArch64][GlobalISel] Legalization for small anyext/sext/zext (#86438)
Similar to #85625, some of the codegen is still far from optimal but
this helps fix quite a few fallback cases.
2024-03-26 09:48:06 +00:00
David Green
4d315ff382 [GlobalISel] Add CTLZ known bits. (#86436)
Replicated from SDAG.
2024-03-26 09:11:35 +00:00
Shilei Tian
0a4299403e [GlobalISel] Fold G_CTTZ if possible (#86224)
This patch tries to fold `G_CTTZ` if possible.
2024-03-25 16:55:37 -04:00
Michael Maitland
9056ce8804 Revert "[RISCV][GISEL] Legalize G_VSCALE"
This reverts commit 47681506de. It is not
consistent with SelectionDAG.
2024-03-25 11:46:02 -07:00
Michael Maitland
47681506de [RISCV][GISEL] Legalize G_VSCALE
G_VSCALE should be lowered using VLENB.
2024-03-25 10:44:58 -07:00
Harvin Iriawan
57146daeaa [CodeGen] Update for scalable MemoryType in MMO (#70452)
Remove getSizeOrUnknown call when MachineMemOperand is created.  For Scalable
TypeSize, the MemoryType created becomes a scalable_vector.

2 MMOs that have scalable memory access can then use the updated BasicAA that
understands scalable LocationSize.

Original Patch by Harvin Iriawan
Co-authored-by: David Green <david.green@arm.com>
2024-03-23 12:56:25 +00:00
Evgenii Kudriashov
d365a45cb3 [GlobalISel] Introduce G_TRAP, G_DEBUGTRAP, G_UBSANTRAP (#84941)
Here we introduce three new GMIR instructions to cover a set of trap
intrinsics. The idea behind it is that generic intrinsics shouldn't be
used with G_INTRINSIC opcode.

These new instructions can match perfectly with existing trap ISD nodes.
It allows X86, AArch64, RISCV and Mips to reuse SelectionDAG patterns for
selection and avoid manual selection. However AMDGPU is an exception. It
selects traps during legalization regardless SelectionDAG or GlobalISel.

Since there are not many places where traps are used, this change
attempts to clean up all the usages of G_INTRINSIC with trap intrinsics. So,
there is no stage when both G_TRAP and
G_INTRINSIC_W_SIDE_EFFECTS(@llvm.trap) are allowed.
2024-03-23 13:12:44 +01:00
Yingwei Zheng
6c1932ffd8 [LLVM] Pass APInt by const reference. NFC. (#86278)
This patch adjusts argument passing for `APInt` to improve the
compile-time.
Compile-time improvement:
https://llvm-compile-time-tracker.com/compare.php?from=d1f182c895728d89c5c3d198b133e212a5d9d4a3&to=32d6611af69bf4e76373f9bc7d9649650f760e48&stat=instructions:u
2024-03-23 14:57:35 +08:00
Madhur Amilkanthwar
7bb87d5338 [AArch64][GlobalISel] Take abs scalar codegen closer to SDAG (#84886)
This patch improves codegen for scalar (<128bits) version
of llvm.abs intrinsic by using the existing non-XOR based lowering.
This takes the generated code closer to SDAG.

codegen with GISel for > 128 bit types is not very good
with these method so not doing so.
2024-03-21 09:54:03 +05:30
Thorsten Schütt
deefe3fbc9 [GlobalIsel] Post-review combine ADDO (#85961)
https://github.com/llvm/llvm-project/pull/82927
2024-03-21 03:56:40 +01:00
Stephen Tozer
bdc77d1ecc [RemoveDIs][NFC] Rename DPLabel->DbgLabelRecord (#85918)
This patch renames DPLabel to DbgLabelRecord, in accordance with the
ongoing DbgRecord rename. This rename was fairly trivial, since DPLabel
isn't as widely used as DPValue and has no real conflicts in either its
full or abbreviated name. As usual, the entire replacement was done
automatically, with `s/DPLabel/DbgLabelRecord/` and `s/DPL/DLR/`.
2024-03-20 13:11:28 +00:00
Jiahan Xie
4bf06bebb9 [GISEL][RISCV] IRTranslator for scalable vector load (#80006)
Add IRTranslator for scalable vector load instruction and include
corresponding tests with alignment argument included, which can be
smaller/equal/larger than element size or smaller/equal/larger than the
minimum total vector size.
2024-03-19 20:12:26 -04:00
Stephen Tozer
ffd08c7759 [RemoveDIs][NFC] Rename DPValue -> DbgVariableRecord (#85216)
This is the major rename patch that prior patches have built towards.
The DPValue class is being renamed to DbgVariableRecord, which reflects
the updated terminology for the "final" implementation of the RemoveDI
feature. This is a pure string substitution + clang-format patch. The
only manual component of this patch was determining where to perform
these string substitutions: `DPValue` and `DPV` are almost exclusively
used for DbgRecords, *except* for:

- llvm/lib/target, where 'DP' is used to mean double-precision, and so
appears as part of .td files and in variable names. NB: There is a
single existing use of `DPValue` here that refers to debug info, which
I've manually updated.
- llvm/tools/gold, where 'LDPV' is used as a prefix for symbol
visibility enums.

Outside of these places, I've applied several basic string
substitutions, with the intent that they only affect DbgRecord-related
identifiers; I've checked them as I went through to verify this, with
reasonable confidence that there are no unintended changes that slipped
through the cracks. The substitutions applied are all case-sensitive,
and are applied in the order shown:

```
  DPValue -> DbgVariableRecord
  DPVal -> DbgVarRec
  DPV -> DVR
```

Following the previous rename patches, it should be the case that there
are no instances of any of these strings that are meant to refer to the
general case of DbgRecords, or anything other than the DPValue class.
The idea behind this patch is therefore that pure string substitution is
correct in all cases as long as these assumptions hold.
2024-03-19 20:07:07 +00:00
Sameer Sahasrabuddhe
ec34699f75 [GlobalISel] convergence control tokens and intrinsics (#67006)
[GlobalISel] Implement convergence control tokens and intrinsics in GMIR

In the IR translator, convert the LLVM token type to LLT::token(), which is an
alias for the s0 type. These show up as implicit uses on convergent operations.

Differential Revision: https://reviews.llvm.org/D158147
2024-03-18 10:34:11 +05:30
Dhruv Chawla
843a978b6f [GlobalISel] Add support to moreElementsVector for G_SEXT, G_ZEXT and G_ANYEXT (#85038) 2024-03-18 07:46:17 +05:30
David Green
601e102bdb [CodeGen] Use LocationSize for MMO getSize (#84751)
This is part of #70452 that changes the type used for the external
interface of MMO to LocationSize as opposed to uint64_t. This means the
constructors take LocationSize, and convert ~UINT64_C(0) to
LocationSize::beforeOrAfter(). The getSize methods return a
LocationSize.

This allows us to be more precise with unknown sizes, not accidentally
treating them as unsigned values, and in the future should allow us to
add proper scalable vector support but none of that is included in this
patch. It should mostly be an NFC.

Global ISel is still expected to use the underlying LLT as it needs, and
are not expected to see unknown sizes for generic operations. Most of
the changes are hopefully fairly mechanical, adding a lot of getValue()
calls and protecting them with hasValue() where needed.
2024-03-17 18:15:56 +00:00
Dhruv Chawla
a7f3d17de1 [GlobalISel] Add support for interleave and deinterleave intrinsics to IRTranslator (#85199)
This patch adds support for the @llvm.experimental.vector.{interleave2,
deinterleave2} intrinsics to IRTranslator for fixed-width vector types.
They are lowered to vector shuffles, in roughly the same manner as
SelectionDAG.
2024-03-15 17:18:17 +05:30
Thorsten Schütt
5f774619ea [GlobalIsel] Combine ADDO (#82927)
Perform the requested arithmetic and produce a carry output in addition
to the normal result.

Clang has them as builtins (__builtin_add_overflow_p). The middle end
has intrinsics for them (sadd_with_overflow).

AArch64: ADDS Add and set flags

On Neoverse V2, they run at half the throughput of basic arithmetic and
have a limited set of pipelines.
2024-03-14 12:45:19 +01:00
Shilei Tian
55d4816393 [NFC] Remove trailing white spaces 2024-03-13 20:18:40 -04:00
Michael Maitland
2f400a2fd7 [GISEL] Add G_VSCALE instruction (#84542) 2024-03-12 20:22:49 -04:00
Stephen Tozer
15f3f446c5 [RemoveDIs][NFC] Rename common interface functions for DPValues->DbgRecords (#84793)
As part of the effort to rename the DbgRecord classes, this patch
renames the widely-used functions that operate on DbgRecords but refer
to DbgValues or DPValues in their names to refer to DbgRecords instead;
all such functions are defined in one of `BasicBlock.h`,
`Instruction.h`, and `DebugProgramInstruction.h`.

This patch explicitly does not change the names of any comments or
variables, except for where they use the exact name of one of the
renamed functions. The reason for this is reviewability; this patch can
be trivially examined to determine that the only changes are direct
string substitutions and any results from clang-format responding to the
changed line lengths. Future patches will cover renaming variables and
comments, and then renaming the classes themselves.
2024-03-12 14:53:13 +00:00
Michael Maitland
034cc2f5d0 [GISEL] Add G_INSERT_SUBVECTOR and G_EXTRACT_SUBVECTOR (#84538)
G_INSERT and G_EXTRACT are not sufficient to use to represent both
INSERT/EXTRACT on a subregister and INSERT/EXTRACT on a vector.

We would like to be able to INSERT/EXTRACT on vectors in cases that
INSERT/EXTRACT on vector subregisters are not sufficient, so we add
these opcodes.

I tried to do a patch where we treated G_EXTRACT as both
G_EXTRACT_SUBVECTOR and G_EXTRACT_SUBREG, but ran into an infinite loop
at this
[point](8b5b294ec2/llvm/lib/Target/RISCV/RISCVISelLowering.cpp (L9932))
in the SDAG equivalent code.
2024-03-11 13:47:30 -04:00
Jay Foad
fd3eaf76ba [GISel] Enforce G_PTR_ADD RHS type matching index size for addr space (#84352) 2024-03-09 09:07:22 +00:00
Jay Foad
430de48a61 [GISel] Simplify getConstantVRegValWithLookThrough. NFC. 2024-03-08 12:26:43 +00:00
Amara Emerson
26fa440957 [GlobalISel] Fix yet another pointer type invalid combining issue, this time in tryFoldSelectOfConstants() 2024-03-07 15:58:28 -08:00
Amara Emerson
641b98a0d1 [GlobalISel] Fix crash in tryFoldAndOrOrICmpsUsingRanges() with pointer types. 2024-03-07 12:56:40 -08:00
Benjamin Kramer
b8b434b3e1 [GISEL] Silence unused variable warning. NFC 2024-03-07 20:46:10 +01:00
Michael Maitland
96049fcf4e [GISEL] Add IRTranslation for shufflevector on scalable vector types (#80378)
Recommits llvm/llvm-project#80378 which was reverted in
llvm/llvm-project#84330. The problem was that the change in
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir used
217 as an opcode instead of a regex.
2024-03-07 09:10:03 -08:00
Michael Maitland
552da24843 Revert "[GISEL] Add IRTranslation for shufflevector on scalable vector types" (#84330)
Reverts llvm/llvm-project#80378

causing Buildbot failures that did not show up with check-llvm or CI.
2024-03-07 10:16:31 -05:00
Michael Maitland
2b8aaef09e [GISEL] Add IRTranslation for shufflevector on scalable vector types (#80378)
This patch is stacked on
https://github.com/llvm/llvm-project/pull/80372,
https://github.com/llvm/llvm-project/pull/80307, and
https://github.com/llvm/llvm-project/pull/80306.

ShuffleVector on scalable vector types gets IRTranslate'd to
G_SPLAT_VECTOR since a ShuffleVector that has operates on scalable
vectors is a splat vector where the value of the splat vector is the 0th
element of the first operand, because the index mask operand is the
zeroinitializer (undef and poison are treated as zeroinitializer here).
This is analogous to what happens in SelectionDAG for ShuffleVector.

`buildSplatVector` is renamed to`buildBuildVectorSplatVector`. I did not
make this a separate patch because it would cause problems to revert
that change without reverting this change too.
2024-03-07 09:50:29 -05:00
David Green
8ee7ef6a37 [GlobalISel] Use LocationSize in GISelAddressing. NFC (#83885)
This is similar to #83017 but for the areas in GlobalISel's
LoadStoreOpt, and should help simplify #70452 a little. It will likely
change a little again once the sizes can be scalable.
2024-03-06 16:36:20 +00:00