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20 Commits

Author SHA1 Message Date
Richard Osborne
f18d95f756 [XCore] The RRegs register class is a superset of GRRegs. 
At the time when the XCore backend was added there were some issues with
with overlapping register classes but these all seem to be fixed now.
Describing the register classes correctly allow us to get rid of a
codegen only instruction (LDAWSP_lru6_RRegs) and it means we can
disassemble ru6 instructions that use registers above r11.

llvm-svn: 178782
 2013-04-04 19:57:46 +00:00
Richard Osborne
53fff94527 [XCore] Add missing 2r instructions. 
These instructions are not targeted by the compiler but it is needed for
the MC layer.

llvm-svn: 175407
 2013-02-17 22:38:05 +00:00
Richard Osborne
f5a3ffcba9 [XCore] Add TSETR instruction. 
This instruction is not targeted by the compiler but it is needed for the
MC layer.

llvm-svn: 175406
 2013-02-17 22:32:41 +00:00
Richard Osborne
038d24f90c [XCore] Add missing l2rus instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173634
 2013-01-27 22:28:30 +00:00
Richard Osborne
6b86eec819 Add instruction encodings / disassembly support for l4r instructions. 
llvm-svn: 173501
 2013-01-25 21:55:32 +00:00
Richard Osborne
a520a7dcf3 Use the correct format in the STW / SETPSC instruction names. 
llvm-svn: 173494
 2013-01-25 21:25:12 +00:00
Richard Osborne
a19fa86a70 Add instruction encodings / disassembly support for l5r instructions. 
llvm-svn: 173479
 2013-01-25 20:20:07 +00:00
Richard Osborne
54e311821f Add instruction encodings / disassembly support for l6r instructions. 
llvm-svn: 173288
 2013-01-23 20:08:11 +00:00
Richard Osborne
6e58c6d86d Add instruction encoding / disassembly support for ru6 / lru6 instructions. 
llvm-svn: 173085
 2013-01-21 20:42:16 +00:00
Richard Osborne
4e69724869 Add instruction encodings / disassembly support for l2rus instructions. 
llvm-svn: 172987
 2013-01-20 18:51:15 +00:00
Richard Osborne
9fbf57b26c Add instruction encodings / disassembly support for l3r instructions. 
llvm-svn: 172986
 2013-01-20 18:37:49 +00:00
Richard Osborne
f063fcee7a Add instruction encodings / disassembler support for 2rus instructions. 
llvm-svn: 172985
 2013-01-20 17:22:43 +00:00
Richard Osborne
3fb7395233 Add instruction encodings / disassembly support 3r instructions. 
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.

llvm-svn: 172984
 2013-01-20 17:18:47 +00:00
Richard Osborne
459e35c261 Add instruction encodings / disassembly support for l2r instructions. 
llvm-svn: 170345
 2012-12-17 16:28:02 +00:00
Richard Osborne
c104bf2769 Fix parameter name in prototypes in XCoreDisassembler. 
llvm-svn: 170332
 2012-12-17 13:55:49 +00:00
Richard Osborne
041071c558 Add instruction encodings / disassembly support for rus instructions. 
llvm-svn: 170330
 2012-12-17 13:50:04 +00:00
Richard Osborne
3a0d5cc314 Add instruction encodings / disassembly support for 2r instructions. 
llvm-svn: 170323
 2012-12-17 12:29:31 +00:00
Richard Osborne
4e1e14bccd Update comments to match recommended doxygen style. 
llvm-svn: 170320
 2012-12-17 12:13:41 +00:00
Richard Osborne
1b5562ad8e Add instruction encodings and disassembly for 1r instructions. 
llvm-svn: 170293
 2012-12-16 17:37:34 +00:00
Richard Osborne
e31735a52b Add XCore disassembler. 
Currently there is no instruction encoding info and
XCoreDisassembler::getInstruction() always returns Fail. I intend to add
instruction encodings and tests in follow on commits.

llvm-svn: 170292
 2012-12-16 17:29:14 +00:00