Commit Graph

36475 Commits

Author SHA1 Message Date
Craig Topper
258f874bb9 [AVX512] Make the permd intrinsics take a 32-bit immediate to match the software spec.
llvm-svn: 269579
2016-05-14 21:13:20 +00:00
Saleem Abdulrasool
8df2f49889 ARM: support export directives for Windows
It seems that cl will emit the export directives for Windows ARM targets.  The
fact that it did this had originally been missed and this functionality was
never implemented.  This makes it possible to rely solely on the source code for
indicating what the exported interfaces are and brings us more compatibility
with cl.

llvm-svn: 269574
2016-05-14 18:58:34 +00:00
Elena Demikhovsky
e79b716daf Fixed lowering of _comi_ intrinsics from all sets - SSE/SSE2/AVX/AVX-512
Differential revision http://reviews.llvm.org/D19261

llvm-svn: 269569
2016-05-14 15:06:09 +00:00
Renato Golin
f4917d35c9 Revert "[llc] New diagnostic handler"
This reverts commit r269563. Even though now it passes all LLDB bots
after a local fix, there's a new buildbot it fails with tests that we
hadn't seen locally:

http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules/builds/15647

Adding those tests to the list to investigate.

llvm-svn: 269568
2016-05-14 14:37:11 +00:00
NAKAMURA Takumi
2c8500996d Re-enable llvm/test/ThinLTO/X86/cache.ll.
This reverts;
  r269548, "XFAIL ThinLTO Caching test on Windows."
  r269561, "Rework r269548, "XFAIL ThinLTO Caching test on Windows.", not to use XFAIL, for now."

llvm-svn: 269567
2016-05-14 14:28:17 +00:00
Dima Stepanov
590d7b2e4a Revert changes after test commit.
llvm-svn: 269564
2016-05-14 13:29:52 +00:00
Renato Golin
c001e67baf [llc] New diagnostic handler
Without a diagnostic handler installed, llc's behaviour is to exit on the first
error that it encounters. This is very different from the behaviour of clang
and other front ends, which try to gather as many errors as possible before
exiting.

This commit adds a diagnostic handler to llc, allowing it to find and report
more than one error. The old behaviour is preserved under a flag (-exit-on-error).

Some of the tests fail with the new diagnostic handler, so they have to use the
new flag in order to run under the previous behaviour. Some of these are known
bugs, others need further investigation. Ideally, we should fix the tests and
remove the flag at some point in the future.

Reapplied after fixing the LLDB build that was broken due to the new
DiagnosticSeverity in LLVMContext.h.

Patch by Diana Picus.

llvm-svn: 269563
2016-05-14 13:15:22 +00:00
NAKAMURA Takumi
c50a2a93ae Rework r269548, "XFAIL ThinLTO Caching test on Windows.", not to use XFAIL, for now.
It was passing (and is XPASSing) with --host=linux --target=win32.

llvm-svn: 269561
2016-05-14 12:47:40 +00:00
Daniel Sanders
e160f83f71 [mips] Enable IAS by default for 32-bit MIPS targets (O32).
Summary:
The MIPS IAS can now pass 'ninja check-all', recurse, build a bootable linux
kernel, and pass a variety of LNT testing.

Unfortunately we can't enable it by default for 64-bit targets yet since the N32
ABI is still very buggy and this also means we can't enable it for N64 either
because we can't distinguish between N32 and N64 in the relevant code.

Reviewers: vkalintiris

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D18759
Differential Revision: http://reviews.llvm.org/D18761

llvm-svn: 269560
2016-05-14 12:43:08 +00:00
Dima Stepanov
435072d3e1 Test commt: remove a blank line.
llvm-svn: 269558
2016-05-14 10:30:54 +00:00
Mehdi Amini
66862c2797 XFAIL ThinLTO Caching test on Windows.
I have no idea what's going on on Windows here.

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 269548
2016-05-14 05:38:58 +00:00
Mehdi Amini
ab4a8b6ca3 Add testing in llvm-lto for ThinLTO caching.
Trying to improve code coverage for `make check`

From: mehdi_amini <mehdi_amini@91177308-0d34-0410-b5e6-96231b3b80d8>
llvm-svn: 269545
2016-05-14 05:16:41 +00:00
Mehdi Amini
34b0241b81 Revert "Add testing in llvm-lto for ThinLTO caching."
This reverts commit r269538 and r269542.
"rename()" is expected to fail across filesystems, will handle this.

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 269543
2016-05-14 05:07:44 +00:00
Mehdi Amini
e19c794741 Increase verbosity in the test output to help debugging windows issues
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 269542
2016-05-14 05:01:36 +00:00
Mehdi Amini
dec0e54d58 Add testing in llvm-lto for ThinLTO caching.
Trying to improve code coverage for `make check`

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 269538
2016-05-14 04:41:26 +00:00
Dan Gohman
a01e8bde57 [WebAssembly] Fix legalization of i128 shifts.
compiler-rt/libgcc shift routines expect the shift count to be an i32, so
use i32 as the shift count for shifts that are legalized to libcalls. This
also reverts r268991, now that the signatures are correct.

llvm-svn: 269531
2016-05-14 02:15:47 +00:00
Craig Topper
d8a9c0d120 [AVX512] Fix types for pshufd intrinsics. The immediate is the second argument and the mask is the 4th argument. Also move the 128/256 tests to the right test file.
Prior to this the immediate was a strange 16-bits and the 512-bit intrinsic couldn't receive the full 16 mask bits it needs.

llvm-svn: 269526
2016-05-14 00:47:18 +00:00
Reid Kleckner
0b269748a6 [codeview] Add type stream merging prototype
Summary:
This code is intended to be used as part of LLD's PDB writing. Until
that exists, this is exposed via llvm-readobj for testing purposes.

Type stream merging uses the following algorithm:

- Begin with a new empty stream, and a new empty hash table that maps
  from type record contents to new type index.
- For each new type stream, maintain a map from source type index to
  destination type index.
- For each record, copy it and rewrite its type indices to be valid in
  the destination type stream.
- If the new type record is not already present in the destination
  stream hash table, append it to the destination type stream, assign it
  the next type index, and update the two hash tables.
- If the type record already exists in the destination stream, discard
  it and update the type index map to forward the source type index to
  the existing destination type index.

Reviewers: zturner, ruiu

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D20122

llvm-svn: 269521
2016-05-14 00:02:53 +00:00
Marcin Koscielnicki
a4fcd3681f [MSan] [PowerPC] Implement PowerPC64 vararg helper.
Differential Revision: http://reviews.llvm.org/D20000

llvm-svn: 269518
2016-05-13 23:55:33 +00:00
Davide Italiano
9922344178 [PM] Port LowerAtomic to the new pass manager.
llvm-svn: 269511
2016-05-13 22:52:35 +00:00
Adam Nemet
c62e554e9a [LAA] Include MaxSafeDepDistBytes in the analysis print-out
llvm-svn: 269508
2016-05-13 22:49:13 +00:00
Michael Zolotukhin
963a6d9c69 Revert "Revert "[Unroll] Implement a conservative and monotonically increasing cost tracking system during the full unroll heuristic analysis that avoids counting any instruction cost until that instruction becomes "live" through a side-effect or use outside the...""
This reverts commit r269395.

Try to reapply with a fix from chapuni.

llvm-svn: 269486
2016-05-13 21:23:25 +00:00
Rui Ueyama
1f6b6e2c53 pdbdump: Print "Publics" stream.
Publics stream seems to contain information as to public symbols.
It actually contains a serialized hash table along with fixed-sized
headers. This patch is not complete. It scans only till the end of
the stream and dump the header information. I'll write code to
de-serialize the hash table later.

Reviewers: zturner

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D20256

llvm-svn: 269484
2016-05-13 21:21:53 +00:00
Jan Vesely
1680039a7a AMDGPU/R600: Fold global address operand
Reviewers: tstellard

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D19793

llvm-svn: 269480
2016-05-13 20:39:31 +00:00
Jan Vesely
f97de00745 AMDGPU/R600: Implement memory loads from constant AS
Reviewers: tstellard

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D19792

llvm-svn: 269479
2016-05-13 20:39:29 +00:00
Steven Wu
25a7330cc8 Disable test from r269436 on unsupported platforms
Fixing bots failure. test/ExecutionEngine/RuntimeDyld/SystemZ/cfi-relo-pc64.s
requires SystemZ backend. Mark the test as unsupported if the backend is not
available.

llvm-svn: 269470
2016-05-13 20:10:51 +00:00
Reid Kleckner
4525fbe22a [codeview] Align class and print names of types
Summary: This way we can get rid of one of the fields in the .def file.

Reviewers: llvm-commits

Subscribers: zturner

Differential Revision: http://reviews.llvm.org/D20251

llvm-svn: 269461
2016-05-13 19:37:07 +00:00
Tim Northover
f8b0a7af52 ARM: use callee-saved list in the order they're actually saved.
When setting the frame pointer, the offset from SP is calculated based on the
stack slot it gets allocated, but this slot is in turn based on the order of
the CSR list so that list should match the order we actually save the registers
in. Mostly it did, but in the edge-case of MachO AAPCS targets it was wrong.

llvm-svn: 269459
2016-05-13 19:16:14 +00:00
Krzysztof Parzyszek
0f791f44c7 [Hexagon] Remove dead nodes from SelectionDAG to avoid cycles
Recent changes to the instruction selection code exposed a problem where
a dead node was not removed on time. This node had both input and output
chains, which lead to an apparent cycle.

llvm-svn: 269458
2016-05-13 18:48:15 +00:00
Konstantin Zhuravlyov
e3d322af57 [AMDGPU] Update nop insertion for debugger usage
- Insert one nop for each high level statement instead of two
- Do not insert nop before prologue

Differential Revision: http://reviews.llvm.org/D20215

llvm-svn: 269452
2016-05-13 18:21:28 +00:00
Renato Golin
1d1b82cbeb Revert "[ARM,AArch64] NFC. Add extra test cases for bswap lowering."
This reverts commit r269425, as it fails on Windows (Thumb only).

llvm-svn: 269451
2016-05-13 18:19:42 +00:00
Sanjay Patel
23fa090738 regenerate checks and add a run to show missed shrinkage
llvm-svn: 269449
2016-05-13 18:04:39 +00:00
Sanjay Patel
4e0cf49318 regenerate checks
llvm-svn: 269447
2016-05-13 18:02:16 +00:00
Paul Osmialowski
4f5b3be7f1 add support for -print-imm-hex for AArch64
Most immediates are printed in Aarch64InstPrinter using 'formatImm' macro,
but not all of them.

Implementation contains following rules:

- floating point immediates are always printed as decimal
- signed integer immediates are printed depends on flag settings
  (for negative values 'formatImm' macro prints the value as i.e -0x01
  which may be convenient when imm is an address or offset)
- logical immediates are always printed as hex
- the 64-bit immediate for advSIMD, encoded in "a:b:c:d:e:f:g:h" is always printed as hex
- the 64-bit immedaite in exception generation instructions like:
  brk, dcps1, dcps2, dcps3, hlt, hvc, smc, svc is always printed as hex
- the rest of immediates is printed depends on availability
  of -print-imm-hex

Signed-off-by: Maciej Gabka <maciej.gabka@arm.com>
Signed-off-by: Paul Osmialowski <pawel.osmialowski@arm.com>

Differential Revision: http://reviews.llvm.org/D16929

llvm-svn: 269446
2016-05-13 18:00:09 +00:00
Reid Kleckner
bab3fab806 [codeview] Dump the type index on the first line of each record
This will make it easier to write FileCheck tests.

llvm-svn: 269444
2016-05-13 17:48:24 +00:00
Chris Bieneman
8b5906ea7f [obj2yaml] [yaml2obj] Basic support for MachO::load_command
This patch adds basic support for MachO::load_command. Load command types and sizes are encoded in the YAML and expanded back into MachO.

The YAML doesn't yet support load command structs, that is coming next. In the meantime as a temporary measure when writing MachO files the load commands are padded with zeros so that the generated binary is valid.

llvm-svn: 269442
2016-05-13 17:41:41 +00:00
Sanjay Patel
0c8f3f9332 [InstCombine] handle zero constant vectors for LE/GE comparisons too
Enhancement to: http://reviews.llvm.org/rL269426
With discussion in: http://reviews.llvm.org/D17859

This should complete the fixes for: PR26701, PR26819:
https://llvm.org/bugs/show_bug.cgi?id=26701
https://llvm.org/bugs/show_bug.cgi?id=26819
 

llvm-svn: 269439
2016-05-13 17:28:12 +00:00
Bryan Chan
d1145ad253 [RuntimeDyld] Support R_390_PC64 relocation type
Summary: When the MCJIT generates ELF code, some DWARF data requires 64-bit PC-relative relocation (R_390_PC64). This patch adds support for R_390_PC64 relocation to RuntimeDyld::resolveSystemZRelocation, to avoid an assertion failure.

Reviewers: uweigand

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D20033

llvm-svn: 269436
2016-05-13 17:23:48 +00:00
Jun Bum Lim
f28beac419 [MemCpyOpt] Use MaxIntSize in byte instead of bit
Summary: This change fix the bug in isProfitableToUseMemset() where MaxIntSize shoule be in byte, not bit.

Reviewers: arsenm, joker.eph, mcrosier

Subscribers: mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D20176

llvm-svn: 269433
2016-05-13 16:52:24 +00:00
Renato Golin
e9fa3585c5 Revert "[llc] New diagnostic handler"
This reverts commit r269428, as it breaks the LLDB build. We need to
understand how to change LLDB in the same way as LLC before landing this
again.

llvm-svn: 269432
2016-05-13 16:02:44 +00:00
Renato Golin
d7a64a5b23 [llc] New diagnostic handler
Without a diagnostic handler installed, llc's behaviour is to exit on the first
error that it encounters. This is very different from the behaviour of clang
and other front ends, which try to gather as many errors as possible before
exiting.

This commit adds a diagnostic handler to llc, allowing it to find and report
more than one error. The old behaviour is preserved under a flag (-exit-on-error).

Some of the tests fail with the new diagnostic handler, so they have to use the
new flag in order to run under the previous behaviour. Some of these are known
bugs, others need further investigation. Ideally, we should fix the tests and
remove the flag at some point in the future.

Patch by Diana Picus.

llvm-svn: 269428
2016-05-13 15:37:46 +00:00
Sanjay Patel
b79ab27853 [InstCombine] canonicalize* LE/GE vector integer comparisons to LT/GT (PR26701, PR26819)
*We don't currently handle the  edge case constants (min/max values), so it's not a complete
canonicalization.

To fully solve the motivating bugs, we need to enhance this to recognize a zero vector
too because that's a ConstantAggregateZero which is a ConstantData, not a ConstantVector
or a ConstantDataVector.

Differential Revision: http://reviews.llvm.org/D17859 

llvm-svn: 269426
2016-05-13 15:10:46 +00:00
Renato Golin
8793c521bc [ARM,AArch64] NFC. Add extra test cases for bswap lowering.
These tests were sitting in Phab for many months. They're good tests and should be in.

Patch by Charlie Turner.

llvm-svn: 269425
2016-05-13 15:10:24 +00:00
Simon Pilgrim
217b886b10 [X86][AVX512] Moved CHECKs inside functions to stop update_llc_test_checks going haywire
I'm not going to regenerate these anytime soon but do have some diffs to apply that I'd like to do with update_llc_test_checks

llvm-svn: 269420
2016-05-13 14:47:55 +00:00
Amjad Aboud
78b1fb0146 Assure calling "cld" instruction in prologue of X86 interrupt handler function.
Differential Revision: http://reviews.llvm.org/D18725

llvm-svn: 269413
2016-05-13 12:46:57 +00:00
Daniel Sanders
e91e52671a [mips][ias] Work around yet another incorrect microMIPS relocation evaluation exposed by r268900.
It's not entirely clear why R_MICROMIPS_(GOT|HI16|LO16) are evaluated
incorrectly in a small number of the LNT tests at this point. However, it's not
related to the STO_MIPS_MICROMIPS issue.

At this point all the microMIPS-related changes of r268900 have been reverted.

llvm-svn: 269410
2016-05-13 12:07:14 +00:00
Hrvoje Varga
6f09cdfd48 [mips][microMIPS] Implement APPEND, BPOSGE32C, MODSUB, MULSA.W.PH and MULSAQ_S.W.PH instructions
Differential Revision: http://reviews.llvm.org/D14117

llvm-svn: 269408
2016-05-13 11:32:53 +00:00
Michael Zolotukhin
9be3b8b9bb Revert "[Unroll] Implement a conservative and monotonically increasing cost tracking system during the full unroll heuristic analysis that avoids counting any instruction cost until that instruction becomes "live" through a side-effect or use outside the..."
This reverts commit r269388.

It caused some bots to fail, I'm reverting it until I investigate the
issue.

llvm-svn: 269395
2016-05-13 06:32:25 +00:00
Matt Arsenault
999f7dd84c AMDGPU: Remove verifier check for scc live ins
We only really need this to be true for SIFixSGPRCopies.
I'm not sure there's any way this could happen before that point.

Fixes a case where MachineCSE could introduce a cross block
scc use.

llvm-svn: 269391
2016-05-13 04:15:48 +00:00
Michael Zolotukhin
b7b8052982 [Unroll] Implement a conservative and monotonically increasing cost tracking system during the full unroll heuristic analysis that avoids counting any instruction cost until that instruction becomes "live" through a side-effect or use outside the...
Summary:
...loop after the last iteration.

This is really hard to do correctly. The core problem is that we need to
model liveness through the induction PHIs from iteration to iteration in
order to get the correct results, and we need to correctly de-duplicate
the common subgraphs of instructions feeding some subset of the
induction PHIs. All of this can be driven either from a side effect at
some iteration or from the loop values used after the loop finishes.

This patch implements this by storing the forward-propagating analysis
of each instruction in a cache to recall whether it was free and whether
it has become live and thus counted toward the total unroll cost. Then,
at each sink for a value in the loop, we recursively walk back through
every value that feeds the sink, including looping back through the
iterations as needed, until we have marked the entire input graph as
live. Because we cache this, we never visit instructions more than twice
-- once when we analyze them and put them into the cache, and once when
we count their cost towards the unrolled loop. Also, because the cache
is only two bits and because we are dealing with relatively small
iteration counts, we can store all of this very densely in memory to
avoid this from becoming an excessively slow analysis.

The code here is still pretty gross. I would appreciate suggestions
about better ways to factor or split this up, I've stared too long at
the algorithmic side to really have a good sense of what the design
should probably look at.

Also, it might seem like we should do all of this bottom-up, but I think
that is a red herring. Specifically, the simplification power is *much*
greater working top-down. We can forward propagate very effectively,
even across strange and interesting recurrances around the backedge.
Because we use data to propagate, this doesn't cause a state space
explosion. Doing this level of constant folding, etc, would be very
expensive to do bottom-up because it wouldn't be until the last moment
that you could collapse everything. The current solution is essentially
a top-down simplification with a bottom-up cost accounting which seems
to get the best of both worlds. It makes the simplification incremental
and powerful while leaving everything dead until we *know* it is needed.

Finally, a core property of this approach is its *monotonicity*. At all
times, the current UnrolledCost is a conservatively low estimate. This
ensures that we will never early-exit from the analysis due to exceeding
a threshold when if we had continued, the cost would have gone back
below the threshold. These kinds of bugs can cause incredibly hard to
track down random changes to behavior.

We could use a techinque similar (but much simpler) within the inliner
as well to avoid considering speculated code in the inline cost.

Reviewers: chandlerc

Subscribers: sanjoy, mzolotukhin, llvm-commits

Differential Revision: http://reviews.llvm.org/D11758

llvm-svn: 269388
2016-05-13 01:42:39 +00:00