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3701 Commits

Author SHA1 Message Date
Craig Topper
fc07498e4a [AVX512] Masked pcmpeqd, pcmpeqq, pcmpgtd, and pcmpgtq don't require avx512bw, just avx512vl. 
llvm-svn: 272532
 2016-06-13 04:15:11 +00:00
Simon Pilgrim
778a7eddb5 [X86][BMI] Improved bmi intrinsics checks 
Ready for matching with llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll (to be added shortly)

llvm-svn: 272490
 2016-06-11 22:40:01 +00:00
Craig Topper
46422562f5 [AVX512] Use a regular expression instead of checking for a specific name in a CHECK line in test. 
llvm-svn: 272470
 2016-06-11 13:35:43 +00:00
Craig Topper
7cc9263ec2 [AVX512] Implement masked and 512-bit pshufd intrinsics directly with __builtin_shufflevector and __builtin_ia32_select. 
llvm-svn: 272467
 2016-06-11 12:50:19 +00:00
Chandler Carruth
c41e081f71 Fix this test to handle NDEBUG builds which don't have a name for the 
basic block.

llvm-svn: 272456
 2016-06-11 06:32:56 +00:00
Craig Topper
68738332b8 [AVX512] Implement 512-bit and masked shufflelo and shufflehi intrinsics directly with __builtin_shufflevector and __builtin_ia32_select. Also improve the formatting of the AVX2 version. 
llvm-svn: 272452
 2016-06-11 03:31:13 +00:00
Craig Topper
d4273a425e [AVX512] Add _mm512_bsrli_epi128 and _mm512_bslli_epi128 intrinsics. 
llvm-svn: 272451
 2016-06-11 03:31:07 +00:00
Pirama Arumuga Nainar
8b788d013c RenderScript support in the Frontend 
Summary:

Create a new Frontend LangOpt to specify the renderscript language. It
is enabled by the "-x renderscript" option from the driver.

Add a "kernel" function attribute only for RenderScript (an "ignored
attribute" warning is generated otherwise).

Make the NativeHalfType and NativeHalfArgsAndReturns LangOpts be implied
by the RenderScript LangOpt.

Reviewers: rsmith

Subscribers: cfe-commits, srhines

Differential Revision: http://reviews.llvm.org/D21198

llvm-svn: 272342
 2016-06-09 23:34:20 +00:00
Craig Topper
2769bb5753 [X86] Handle AVX2 pslldqi and psrldqi intrinsics shufflevector creation directly in the header file instead of in CGBuiltin.cpp. Simplify the sse2 equivalents as well. 
llvm-svn: 272246
 2016-06-09 05:15:12 +00:00
Vitaly Buka
9d1b12c091 Specify target in lifetime-asan test. 
Summary: Some target platforms -fsanitize=address.

Reviewers: pcc, eugenis

Subscribers: cfe-commits, christof, chapuni, kubabrecka

Differential Revision: http://reviews.llvm.org/D21117

llvm-svn: 272185
 2016-06-08 18:18:08 +00:00
Chris Dewhurst
ea61147fc7 [Sparc] Complex return value ABI compliance. 
According to the Sparc V8 ABI, complex numbers should be passed and returned as pairs of registers:

https://docs.oracle.com/cd/E26502_01/html/E28387/gentextid-2734.html

This fix ensures this is the case. Without this, complex numbers are returned as a struct of two floats, which breaks the ABI rules.

Differential Review: http://reviews.llvm.org/D20955

llvm-svn: 272148
 2016-06-08 14:46:05 +00:00
Igor Breger
aadb876200 [AVX512] Emit select instruction instead of using x86 specific instrinsics. 
This will allow us to remove the x86 instrinics from the backend.

Differential Revision: http://reviews.llvm.org/D21060

llvm-svn: 272141
 2016-06-08 13:59:20 +00:00
Michael Zuckerman
c4ae8537cf [Clang][AVX512][BUILTIN]Adding intrinsics for range_round_{sd|ss} 
Differential Revision: http://reviews.llvm.org/D21002

llvm-svn: 272123
 2016-06-08 08:19:27 +00:00
Michael Zuckerman
96d0399658 [clang][AVX512][Intrinsics] Adding intrinsics reduce_[round]_{ss|sd} to clang 
Differential Revision: http://reviews.llvm.org/D21014

llvm-svn: 272012
 2016-06-07 14:00:20 +00:00
Craig Topper
f51cc07719 [AVX512] Convert masked palignr builtins directly to native IR similar to the other palignr builtins, but with a select to handle masking. 
llvm-svn: 271873
 2016-06-06 06:13:01 +00:00
Michael Zuckerman
95721ac863 [Clang][AVX512]Adding set4 intrinsics 
Differential Revision: http://reviews.llvm.org/D20866

llvm-svn: 271835
 2016-06-05 15:43:30 +00:00
Michael Zuckerman
f36f6eb036 [Clang][AVX512][Intrinsics] Adding two definitions _mm512_setzero and _mm512_setzero_epi32 
Differential Revision: http://reviews.llvm.org/D20871

llvm-svn: 271832
 2016-06-05 15:12:52 +00:00
Craig Topper
4d302448ae [AVX512] Remove 512-bit andnot tests from the avx512vl test file. 
llvm-svn: 271795
 2016-06-04 16:37:38 +00:00
NAKAMURA Takumi
7f74dedb39 Suppress clang/test/CodeGen/lifetime-asan.c for targeting mingw. 
clang.EXE: error: unsupported option '-fsanitize=address' for target 'x86_64-w64-windows-gnu'

llvm-svn: 271509
 2016-06-02 10:54:45 +00:00
Sjoerd Meijer
90df4a7c31 This adds target support and tests for Cortex-A73 
Differential Revision: http://reviews.llvm.org/D20864

llvm-svn: 271507
 2016-06-02 10:48:37 +00:00
Asaf Badouh
89f657611c [X86][AVX512] add intrinsics of Scalar FP to integer 
Differential Revision: http://reviews.llvm.org/D20861

llvm-svn: 271499
 2016-06-02 08:11:35 +00:00
Michael Zuckerman
9e7d0a98fa [Clang][AVX512][INTRINSICS] adding round cvt and fix regular cvtps_ph 
Differential Revision: http://reviews.llvm.org/D20870

llvm-svn: 271498
 2016-06-02 07:44:08 +00:00
Vitaly Buka
9d4eb6f389 [asan] Added -fsanitize-address-use-after-scope flag 
Summary:
Also emit lifetime markers for -fsanitize-address-use-after-scope.
Asan uses life-time markers for use-after-scope check.

PR27453

Reviewers: kcc, eugenis, aizatsky

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D20759

llvm-svn: 271451
 2016-06-02 00:24:20 +00:00
Simon Pilgrim
00880511b1 [X86][SSE] Replace (V)CVTTPS2DQ and VCVTTPD2DQ truncating (round to zero) f32/f64 to i32 with generic IR (clang) 
The 'cvtt' truncation (round to zero) conversions can be safely represented as generic __builtin_convertvector (fptosi) calls instead of x86 intrinsics. We already do this (implicitly) for the scalar equivalents.

Note: I looked at updating _mm_cvttpd_epi32 as well but this still requires a lot more backend work to correctly lower (both for debug and optimized builds).

Differential Revision: http://reviews.llvm.org/D20859

llvm-svn: 271436
 2016-06-01 21:46:51 +00:00
Michael Zuckerman
6170c15fc6 [Clang][Intrinsics][avx512] Continue Adding round cvt to clang 
And remove trailing spaces in intrinsic f test
Differential Revision: http://reviews.llvm.org/D20810

llvm-svn: 271398
 2016-06-01 14:41:41 +00:00
Michael Zuckerman
e54093fcc0 Adding front-end support to several intrinsics (bit scanning, conversion and state reading intrinsics) 
Adding LLVM front-end support to two intrinsics dealing with bit scan: _bit_scan_forward and _bit_scan_reverse.
 Their functionality is as described in Intel intrinsics guide:
 https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_forward&expand=371,370
 https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_reverse&expand=371,370

 Furthermore, adding clang front-end support to these conversion intrinsics: _mm256_cvtsd_f64, _mm256_cvtsi256_si32 and _mm256_cvtss_f32.

 Finally, adding tests to all of the above, as well as to the state reading intrinsics _rdpmc and _rdtsc.
  Their functionality is also specified in the Intel intrinsics guide.


Commit on behalf of Omer Paparo Bivas

llvm-svn: 271387
 2016-06-01 12:21:00 +00:00
Michael Zuckerman
e6aa66a53d [Clang][Intrinsics][avx512] Adding round intrinsics fot max/min/sqrt instruction set to clang 
Differential Revision: http://reviews.llvm.org/D20812

llvm-svn: 271373
 2016-06-01 08:34:03 +00:00
Michael Zuckerman
c301c194ec [Clang][Intrinsics][avx512] Adding round roundscale to clang 
Differential Revision: http://reviews.llvm.org/D20815

llvm-svn: 271368
 2016-06-01 07:35:44 +00:00
Saleem Abdulrasool
4976634208 CodeGen: tweak CFString emission for COFF targets 
The `isa' member was previously not given the correct DLL Storage.  Ensure that
we give the `isa' constant `__CFConstantStringClassReference' the correct DLL
storage.  Default to dllimport unless an explicit specification gives it a
dllexport storage.

llvm-svn: 271361
 2016-06-01 04:22:24 +00:00
Matt Arsenault
6dc455fb93 AMDGPU: Update datalayout string 
llvm-svn: 271297
 2016-05-31 16:58:18 +00:00
Ranjeet Singh
61c47fd86a [ARM] Add load/store co-processor intrinsics. 
Differential Revision: http://reviews.llvm.org/D20563

llvm-svn: 271275
 2016-05-31 13:31:25 +00:00
Michael Zuckerman
186d86738d [Clang][Intrinsics][avx512] Adding round cvt to clang 
Differential Revision: http://reviews.llvm.org/D20790

llvm-svn: 271265
 2016-05-31 11:27:34 +00:00
Craig Topper
4b060e31c9 [AVX512] Convert masked load builtins to generic masked load intrinsics instead of the x86 specific ones. 
This will allow the x86 intrinsics to be removed from the backend.

llvm-svn: 271253
 2016-05-31 06:58:07 +00:00
Craig Topper
6e891fbdd2 [AVX512] Emit generic masked store instrinsics instead of using x86 specific intrinsics. 
This will allow us to remove the x86 instrinics from the backend.

llvm-svn: 271246
 2016-05-31 01:50:10 +00:00
Simon Pilgrim
0e90936fea [X86] Ensure load/store tests unaligned pointers really are align 1 
llvm-svn: 271227
 2016-05-30 19:20:55 +00:00
Simon Pilgrim
43439bd33d [X86][SSE] Added missing tests (merge failure) 
Differential Revision: http://reviews.llvm.org/D20617

llvm-svn: 271219
 2016-05-30 17:58:38 +00:00
Simon Pilgrim
645e1ad33a [X86][SSE] _mm_store1_ps/_mm_store1_pd should require an aligned pointer 
According to the gcc headers, intel intrinsics docs and msdn codegen the _mm_store1_pd (and its _mm_store_pd1 equivalent) should use an aligned pointer - the clang headers are the only implementation I can find that assume non-aligned stores (by storing with _mm_storeu_pd).

Additionally, according to the intel intrinsics docs and msdn codegen the _mm_store1_ps (_mm_store_ps1) requires a similarly aligned pointer.

This patch raises the alignment requirements to match the other implementations by calling _mm_store_ps/_mm_store_pd instead.

I've also added the missing _mm_store_pd1 intrinsic (which maps to _mm_store1_pd like _mm_store_ps1 does to _mm_store1_ps).

As a followup I'll update the llvm fast-isel tests to match this codegen.

Differential Revision: http://reviews.llvm.org/D20617

llvm-svn: 271218
 2016-05-30 17:55:25 +00:00
Craig Topper
09175dab31 [X86] Replace unaligned store builtins in SSE/AVX intrinsic files with code that will compile to a native unaligned store. Remove the builtins since they are no longer used. 
Intrinsics will be removed from llvm in a future commit.

llvm-svn: 271214
 2016-05-30 17:10:30 +00:00
Saleem Abdulrasool
2460a36f53 test: add explicit targets for some tests 
These tests currently expect MachO section names and do not provide a target.
Explicitly provide one.

llvm-svn: 271212
 2016-05-30 16:36:48 +00:00
Saleem Abdulrasool
f7444e645b CodeGen: tweak CFConstantStrings for COFF and ELF 
Adjust the constant CFString emission to emit into more appropriate sections on
ELF and COFF targets.  It would previously try to use MachO section names
irrespective of the file format.

llvm-svn: 271211
 2016-05-30 16:23:07 +00:00
Michael Zuckerman
9fcf3552ad [Clang][avx512][builtin] Adding missing intrinsics for cvt 
Differential Revision: http://reviews.llvm.org/D20618

llvm-svn: 271205
 2016-05-30 13:22:12 +00:00
Rafael Espindola
ab3e10a7a0 Mark test as requiring x86-registered-target. 
llvm-svn: 271163
 2016-05-29 02:36:16 +00:00
Rafael Espindola
f8f01c3d59 Handle -Wa,--mrelax-relocations=[no|yes]. 
llvm-svn: 271162
 2016-05-29 02:01:14 +00:00
Saleem Abdulrasool
442b88b9ec CodeGen: support blocks on COFF targets in DLLs 
This extends the blocks support to support blocks with a dynamically linked
blocks runtime.  The previous code generation would work only for static builds
of the blocks runtime.  Mark the block "isa" pointers and functions as dllimport
if no explicit declaration marked with __declspec(dllexport) is found.  This
additional check allows for the use of the functionality in the runtime library
if desired.

llvm-svn: 271138
 2016-05-28 19:41:35 +00:00
Craig Topper
cbdbbac875 [AVX512] Add masked v16i32 and v8i64 unaligned store tests. 
llvm-svn: 271134
 2016-05-28 18:59:06 +00:00
Simon Pilgrim
91b77ceaed [X86][SSE] Replace VPMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (clang) 
The VPMOVSX and (V)PMOVZX sign/zero extension intrinsics can be safely represented as generic __builtin_convertvector calls instead of x86 intrinsics.

This patch removes the clang builtins and their use in the sse2/avx headers - a companion patch will remove/auto-upgrade the llvm intrinsics.

Note: We already did this for SSE41 PMOVSX sometime ago.

Differential Revision: http://reviews.llvm.org/D20684

llvm-svn: 271106
 2016-05-28 08:12:45 +00:00
David Majnemer
e6abf3d29f [CodeGen] Don't crash when sizeof(long) != 4 for some intrins 
_InterlockedIncrement and _InterlockedDecrement have 'long' in their
prototypes.  We assumed 'long' was the same size as an i32 which is
incorrect for other targets.

This fixes PR27892.

llvm-svn: 270953
 2016-05-27 02:06:19 +00:00
Michael Zuckerman
22c47e606a Adding missing _mm512_castsi512_si256 intrinsic. 
llvm-svn: 270851
 2016-05-26 14:32:11 +00:00
Simon Pilgrim
1fdfbf6941 [X86][F16C] Improved f16c intrinsics checks 
Added checks for upper elements being zero'd in scalar conversions

llvm-svn: 270836
 2016-05-26 10:20:25 +00:00
Simon Pilgrim
57446efaa9 [X86][AVX2] Improved checks for float/double mask generation for non-masked gathers 
llvm-svn: 270833
 2016-05-26 09:56:50 +00:00