564d47db9e
Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable abs and neg modifiers for v_cndmask_b32 (https://reviews.llvm.org/D135900). - Correct v_mov_b32_sdwa (it does not support abs and neg input modifiers yet). - Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783). - Minor corrections and improvements.
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* Automatically generated file, do not edit! *
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.. _amdgpu_synid_gfx8_vdata_629a92:
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vdata
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=====
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Image data to store by an *image_store* instruction.
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*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
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* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits, depending on :ref:`d16<amdgpu_synid_d16>`.
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* :ref:`d16<amdgpu_synid_d16>` has different meanings for GFX8.0 and GFX8.1:
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* For GFX8.0, this modifier does not affect the size of data elements in registers. Values in registers are stored in low 16 bits, high 16 bits are unused. There is no packing.
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* Starting from GFX8.1, this modifier specifies that values in registers are packed; each value occupies 16 bits.
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*Operands:* :ref:`v<amdgpu_synid_v>`
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