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Rahul Joshi d7b8b65e23 [LLVM][TableGen][DecoderEmitter] Add wrapper struct for bit_value_t (#146248) 
Add a convenience wrapper struct for the `bit_value_t` enum type to host
various constructors, query, and printing support. Also refactor related
code in several places. In `getBitsField`, use `llvm::append_range` and
`SmallVector::append()` and eliminate manual loops. Eliminate
`emitNameWithID` and instead use the `operator <<` that does the same
thing as this function. Have `BitValue::getValue()` (replacement for
`Value`) return std::optional<> instead of -1 for unset bits. Terminate
with a fatal error when a decoding conflict is encountered.
2025-07-01 07:36:17 -07:00
..
Common
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CompressInstEmitter
[TableGen][RISCV] Support sub-operands in CompressInstEmitter.cpp. (#133039)
2025-03-27 19:10:40 -07:00
FixedLenDecoderEmitter
[LLVM][TableGen][DecoderEmitter] Add wrapper struct for bit_value_t (#146248)
2025-07-01 07:36:17 -07:00
GlobalISelCombinerEmitter
Reland [llvm] Add support for llvm IR atomicrmw fminimum/fmaximum instructions (#137701)
2025-04-30 22:06:37 +01:00
GlobalISelEmitter
[GlobalISel] Fixes unused variable error in testMOPredicate_MO (#143364)
2025-06-09 13:37:38 +01:00
SDNodeInfoEmitter
[StrTable] Switch intrinsics to StringTable and work around MSVC (#123548)
2025-01-28 00:17:04 -08:00
64-bit-int.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
2003-08-03-PassCode.td
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2006-09-18-LargeInt.td
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2010-03-24-PrematureDefaults.td
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AcquireAtCycle.td
[TableGen][MCSched] Update error messages on the range of Acquire/ReleaseAtCycle (#131908)
2025-03-24 13:42:28 -07:00
address-space-patfrags.td
[DAG] Use SDValue for PatFrag checks (#137519)
2025-05-01 08:58:59 +01:00
AliasAsmString.td
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AllowDuplicateRegisterNames.td
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ambiguous-composition.td
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AnonDefinitionOnDemand.td
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anonymous-location.td
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arithmetic.td
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ArtificialSubregs.td
[TableGen] Fix calculation of Lanemask for RCs with artificial subregs. (#114392)
2024-11-04 16:10:50 +00:00
AsmPredicateCombining.td
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AsmPredicateCombiningRISCV.td
[RISCV] Don't convert virtual register Register to MCRegister in isCompressibleInst. (#122843)
2025-01-13 23:36:09 -08:00
AsmPredicateCondsEmission.td
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AsmVariant.td
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AsmWriterPCRelOp.td
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assert.td
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bare-minimum-psets.td
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BigEncoder.td
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BitOffsetDecoder.td
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BitsInit.td
[TableGen] Add assert to validate Objects list for HwModeSelect (#123794)
2025-01-27 13:44:44 -08:00
BitsInitErrors.td
[TableGen] Add assert to validate Objects list for HwModeSelect (#123794)
2025-01-27 13:44:44 -08:00
BitsInitOverflow.td
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cast-list-initializer.td
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cast-multiclass.td
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cast-string.td
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cast-typeerror.td
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cast.td
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cc-assign-to-reg-tuple.td
[TableGen][NFC] Use early exit to simplify large block in emitAction. (#138220)
2025-05-08 12:12:15 -05:00
check-duplicate-tuple-regs.td
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ClassInstanceValue.td
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code.td
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CodeGenSchedule-duplicate-instrw.td
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compare.td
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CompressWriteLatencyEntry.td
[MC] Use StringTable to reduce dynamic relocations (#144202)
2025-06-25 05:23:11 -07:00
ConcatenatedSubregs.td
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cond-bitlist.td
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cond-default.td
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cond-empty-list-arg.td
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cond-inheritance.td
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cond-let.td
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cond-list.td
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cond-subclass.td
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cond-type.td
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cond-usage.td
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condsbit.td
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ConstraintChecking1.td
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ConstraintChecking2.td
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ConstraintChecking3.td
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ConstraintChecking4.td
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ConstraintChecking5.td
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ConstraintChecking6.td
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ConstraintChecking7.td
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ConstraintChecking8.td
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ConstraintChecking.inc
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CStyleComment.td
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dag-functional.td
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dag-isel-complexpattern.td
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dag-isel-instrument.td
[llvm-tblgen] Increase Coverage Index Size (#118329)
2024-12-04 09:19:13 +00:00
dag-isel-regclass-emit-enum.td
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dag-isel-res-order.td
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dag-isel-subregs.td
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dag-subst.td
[TableGen] !subst on a dag should retain name of operator (#141195)
2025-05-23 12:03:56 -07:00
Dag.td
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DAGDefaultOps.td
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DecoderEmitterFnTable.td
[LLVM][DecoderEmitter] Add option to use function table in decodeToMCInst (#144814)
2025-06-24 18:49:05 -07:00
def-multiple-operands.td
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defmclass.td
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DefmInherit.td
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DefmInsideMultiClass.td
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defset-typeerror.td
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defset.td
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deftype.td
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defvar.td
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detailed-records.td
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directive1.td
[utils][TableGen] Handle versions on clause/directive spellings (#143021)
2025-06-06 17:07:25 -05:00
directive2.td
[utils][TableGen] Handle versions on clause/directive spellings (#143021)
2025-06-06 17:07:25 -05:00
directive3.td
[utils][TableGen] Implement clause aliases as alternative spellings (#141765)
2025-06-05 12:35:30 -05:00
dump.td
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duplicate-include.inc
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duplicate-include.td
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DuplicateFieldValues.td
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DuplicateProcessorFeatures.td
[TableGen] Print a warning when a Processor contains duplicate Features / TuneFeatures (#137864)
2025-04-29 16:22:48 -07:00
empty-psets.td
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empty.td
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eq-unset.td
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eq.td
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eqbit.td
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exists-error-non-string.td
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exists-error-record.td
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exists-error-uninitialized.td
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exists.td
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FastISelEmitter.td
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field-access-initializers.td
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FieldAccess.td
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filter.td
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find.td
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foldl.td
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foreach-eval.td
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foreach-leak.td
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foreach-multiclass.td
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foreach-range-parse-errors0.td
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foreach-range-parse-errors1.td
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foreach-range-parse-errors2.td
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foreach-range-parse-errors3.td
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foreach-range-parse-errors4.td
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foreach-range-parse-errors5.td
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foreach-variable-range.td
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foreach.td
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ForeachList.td
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ForeachLoop.td
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ForwardRef.td
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GeneralList.td
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generic-tables-instruction.td
[TableGen][NFC] Factor early-out range check. (#123645)
2025-01-20 19:13:31 -06:00
generic-tables-return-range.td
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generic-tables.td
[TableGen][NFC] Factor early-out range check. (#123645)
2025-01-20 19:13:31 -06:00
GenTags.td
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get-named-operand-idx.td
[TableGen] Emit OpName as an enum class instead of a namespace (#125313)
2025-02-12 08:19:30 -08:00
get-operand-type-no-expand.td
[TableGen][InstrInfo] Cull mapping that have not been enabled/not needed (#126137)
2025-02-10 08:16:12 -08:00
get-operand-type.td
[TableGen][InstrInfo] Cull mapping that have not been enabled/not needed (#126137)
2025-02-10 08:16:12 -08:00
getsetop.td
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HasNoUse.td
[DAG] Use SDValue for PatFrag checks (#137519)
2025-05-01 08:58:59 +01:00
HwModeBitSet.td
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HwModeEncodeAPInt.td
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HwModeEncodeDecode2.td
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HwModeEncodeDecode3.td
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HwModeEncodeDecode.td
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HwModeSelect.td
[TableGen] Add assert to validate Objects list for HwModeSelect (#123794)
2025-01-27 13:44:44 -08:00
HwModeSubRegs.td
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if-empty-list-arg.td
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if-type.td
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if-unresolved-cast.td
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if.td
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ifbit.td
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ifstmt.td
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Include.inc
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Include.td
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inhibit-pset.td
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initialized.td
[llvm][TableGen] Add a !initialized predicate to allow testing for ? (#117964)
2024-12-17 20:34:35 -06:00
instances.td
[TableGen] Add !instances operator to get defined records (#129680)
2025-03-28 16:31:00 +08:00
IntBitInit.td
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interleave.td
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intrinsic-attrs.td
[Intrinsics] Add support for range attributes (#135642)
2025-04-17 11:11:00 +02:00
intrinsic-duplicate-name.td
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intrinsic-long-name.td
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intrinsic-overload-conflict.td
[LLVM][TableGen] Refine overloaded intrinsic suffix check (#117957)
2024-12-03 13:33:15 -05:00
intrinsic-prefix-error.td
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intrinsic-struct.td
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intrinsic-target-prefix-for-target-independent.td
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intrinsic-varargs.td
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IntSpecialValues.td
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invalid-macro-name-command-line.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
invalid-type-cast-patfrags.td
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InvalidMCSchedClassDesc.td
[MC] Use StringTable to reduce dynamic relocations (#144202)
2025-06-25 05:23:11 -07:00
isa-non-primary.td
[tblgen] Fix behavior of !isa to prevent premature folding (#130442)
2025-03-18 20:05:37 -07:00
isa.td
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JSON-check.py
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JSON-locs.td
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JSON.td
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LazyChange.td
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LetInsideMultiClasses.td
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letUnknownValue.td
[llvm][TableGen] Fix misleading error for invalid use of let (#118616)
2024-12-09 13:21:46 +00:00
lisp.td
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list-element-bitref.td
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ListArgs.td
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ListArgsSimple.td
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listconcat.td
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ListConversion.td
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listflatten-error.td
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listflatten.td
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ListManip.td
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ListOfList.td
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listpaste.td
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listremove.td
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ListSlices-fail.td
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ListSlices.td
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listsplat.td
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lit.local.cfg
[AIX] Use internal lit shell for TableGen instead of a global setting (#113627)
2024-10-25 13:06:02 -04:00
LoLoL.td
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MacroFusion.td
[TableGen][MacroFusion] Predicate if the first inst has the same register (#137778)
2025-05-13 19:05:42 +08:00
match.td
[TableGen] Add !match operator to do regex matching (#130759)
2025-03-13 12:13:09 +08:00
math.td
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MissingOperandField.td
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MixedCasedMnemonic.td
[StrTable] Switch intrinsics to StringTable and work around MSVC (#123548)
2025-01-28 00:17:04 -08:00
MnemonicAlias.td
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MultiClass-def-fail.td
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MultiClass-defm-fail.td
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MultiClass-defm.td
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MultiClass.td
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MultiClassDefName.td
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MultiClassInherit.td
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MultiPat.td
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multiple-type-casts-patfrags.td
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name-resolution-consistency.td
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named-arguments.td
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nested_ifdef2.inc
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nested_ifdef_main.td
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nested_ifdef.inc
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nested-comment.td
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NestedForeach.td
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nul-char.td
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paste-reserved.td
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Paste.td
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PerWriteCycleCount.td
[TableGen] Add support for per-write cycle tunables (#125870)
2025-02-17 11:32:47 +00:00
pr8330.td
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predicate-patfags.td
[TableGen] Directly use SDNode functions to implement HasOneUse and HasNoUse. NFC (#133976)
2025-04-01 22:14:17 -07:00
prep-diag1.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
prep-diag2.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
prep-diag3.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
prep-diag4.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
prep-diag5.td
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prep-diag6.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
prep-diag7.td
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prep-diag8.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
prep-diag9.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
prep-diag10.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
prep-diag11-include.inc
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prep-diag11.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
prep-diag12-include.inc
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prep-diag12.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
prep-diag13.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
prep-diag14.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
prep-ifndef-diag-1.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
prep-ifndef-diag-2.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
prep-ifndef.td
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prep-region-include.inc
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prep-region-processing.td
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ProcessorUniqueNames.td
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pset-enum.td
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pseudo-inst-expansion.td
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range-lists.td
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range-op-fail.td
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range-op.td
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rc-weight-override.td
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ReadAdvanceInvalidWrite.td
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RegBankFromRegClass.td
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RegisterBankEmitter.td
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RegisterClass.td
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RegisterEncoder.td
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RegisterInfoEmitter-BaseClassOrder.td
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RegisterInfoEmitter-inherit-properties.td
[TableGen] Inherit properties from the nearest allocatable superclass. (#127018)
2025-03-25 15:54:06 -05:00
RegisterInfoEmitter-regcost-list.td
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RegisterInfoEmitter-regcost-tuple.td
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RegisterInfoEmitter-regcost.td
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RegisterInfoEmitter-tsflags.td
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RelTest.td
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repr.td
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riscv-target-def.td
[RISCV] Add mvendorid/marchid/mimpid to CPU definitions (#116202)
2024-11-22 22:58:54 +08:00
RuntimeLibcallEmitter.td
TableGen: Generate enum for runtime libcall implementations (#144973)
2025-06-27 17:40:43 +09:00
SchedModelError.td
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searchabletables-intrinsic.td
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self-reference-recursion.td
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self-reference-typeerror.td
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self-reference.td
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SetTheory.td
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SiblingForeach.td
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simplify-patfrag.td
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size.td
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Slice.td
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spurious-semi.td
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strconcat.td
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string_ops.td
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String.td
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SubRegsAndAliases.td
[TableGen][CodeGen] Give every leaf register a unique regunit (#139526)
2025-05-13 10:52:36 +01:00
subst2.td
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subst.td
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substr.td
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SubtargetFeatureUniqueNames.td
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SuperSubclassSameName.td
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TargetInstrInfo.td
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TargetInstrSpec.td
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template-arg-dependency.td
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template-args.td
[TableGen] Do not exit in template argument check (#121636)
2025-01-06 21:06:17 +01:00
TemplateArgRename.td
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Tree.td
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TreeNames.td
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true-false.td
[TableGen] Avoid evaluating RHS of a BinOp until short-circuit is complete (#144021)
2025-06-13 10:36:09 -07:00
trydecode-emission2.td
[NFC][TableGen] Print DecodeIdx for DecodeOps in DecoderEmitter (#142963)
2025-06-05 21:57:26 -07:00
trydecode-emission3.td
[NFC][TableGen] Print DecodeIdx for DecodeOps in DecoderEmitter (#142963)
2025-06-05 21:57:26 -07:00
trydecode-emission4.td
[NFC][TableGen] Print DecodeIdx for DecodeOps in DecoderEmitter (#142963)
2025-06-05 21:57:26 -07:00
trydecode-emission.td
[NFC][TableGen] Print DecodeIdx for DecodeOps in DecoderEmitter (#142963)
2025-06-05 21:57:26 -07:00
TwoLevelName.td
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UnsetBitInit.td
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unsetop.td
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unterminated-c-comment-include.inc
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unterminated-c-comment.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
unterminated-code-block-include.inc
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unterminated-code-block.td
[LLVM] Change error messages to start with lower case (#113748)
2024-10-29 12:26:33 -07:00
UnterminatedComment.td
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usevalname.td
[TableGen] Add missing $ before the dag operator name (#140969)
2025-05-22 16:21:19 -07:00
ValidIdentifiers.td
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VarLenDecoder.td
[LLVM][MC] Introduce OrFail variants of MCD ops (#138614)
2025-06-05 06:17:50 -07:00
VarLenEncoder.td
[NFC][TableGen] Create valid Dag in VarLenCodeEmitter (#140283)
2025-05-19 12:27:18 -07:00
VarLenEncoderHwModes.td
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warn-unused-template-arg.td
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x86-fold-tables.inc
[X86][NFC] Add missing immediate qualifier to VSM3RNDS2 instruction (#131576)
2025-03-17 17:59:39 +08:00
x86-fold-tables.td
[TableGen] Handle Windows line endings in x86-fold-tables.td test (#112997)
2024-10-21 09:58:59 -07:00
x86-instr-mapping.inc
[X86][NF] Switch the order of Inst and &Target.getInstruction(NewRec) (#130739)
2025-03-12 17:35:54 +08:00
x86-instr-mapping.td
Test added for x86-instr-mapping (#115170)
2024-11-07 19:09:21 +08:00