a57847232f
The tests in this directory all depend on the AMDGPU target being present so we can let opt infer the data layout. Reviewed By: arsenm Pull Request: https://github.com/llvm/llvm-project/pull/137924
51 lines
2.1 KiB
LLVM
51 lines
2.1 KiB
LLVM
; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' -S -o - %s | FileCheck %s
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declare i64 @_Z12get_local_idj(i32)
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declare i64 @_Z12get_group_idj(i32)
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declare double @llvm.fmuladd.f64(double, double, double)
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; CHECK-LABEL: @factorizedVsNonfactorizedAccess(
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; CHECK: load <2 x float>
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; CHECK: store <2 x float>
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define amdgpu_kernel void @factorizedVsNonfactorizedAccess(ptr addrspace(1) nocapture %c) {
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entry:
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%call = tail call i64 @_Z12get_local_idj(i32 0)
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%call1 = tail call i64 @_Z12get_group_idj(i32 0)
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%div = lshr i64 %call, 4
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%div2 = lshr i64 %call1, 3
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%mul = shl i64 %div2, 7
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%rem = shl i64 %call, 3
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%mul3 = and i64 %rem, 120
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%add = or i64 %mul, %mul3
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%rem4 = shl i64 %call1, 7
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%mul5 = and i64 %rem4, 896
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%mul6 = shl nuw nsw i64 %div, 3
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%add7 = add nuw i64 %mul5, %mul6
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%mul9 = shl i64 %add7, 10
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%add10 = add i64 %mul9, %add
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%arrayidx = getelementptr inbounds float, ptr addrspace(1) %c, i64 %add10
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%load1 = load float, ptr addrspace(1) %arrayidx, align 4
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%conv = fpext float %load1 to double
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%mul11 = fmul double %conv, 0x3FEAB481D8F35506
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%conv12 = fptrunc double %mul11 to float
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%conv18 = fpext float %conv12 to double
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%storeval1 = tail call double @llvm.fmuladd.f64(double 0x3FF4FFAFBBEC946A, double 0.000000e+00, double %conv18)
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%cstoreval1 = fptrunc double %storeval1 to float
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store float %cstoreval1, ptr addrspace(1) %arrayidx, align 4
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%add23 = or disjoint i64 %add10, 1
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%arrayidx24 = getelementptr inbounds float, ptr addrspace(1) %c, i64 %add23
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%load2 = load float, ptr addrspace(1) %arrayidx24, align 4
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%conv25 = fpext float %load2 to double
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%mul26 = fmul double %conv25, 0x3FEAB481D8F35506
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%conv27 = fptrunc double %mul26 to float
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%conv34 = fpext float %conv27 to double
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%storeval2 = tail call double @llvm.fmuladd.f64(double 0x3FF4FFAFBBEC946A, double 0.000000e+00, double %conv34)
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%cstoreval2 = fptrunc double %storeval2 to float
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store float %cstoreval2, ptr addrspace(1) %arrayidx24, align 4
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ret void
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}
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