a57847232f
The tests in this directory all depend on the AMDGPU target being present so we can let opt infer the data layout. Reviewed By: arsenm Pull Request: https://github.com/llvm/llvm-project/pull/137924
41 lines
1.9 KiB
LLVM
41 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -mtriple=amdgcn-- -mcpu=tonga -passes=load-store-vectorizer -S -o - %s | FileCheck %s
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@lds = internal addrspace(3) global [512 x float] undef, align 4
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; The original load has an implicit alignment of 4, and should not
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; increase to an align 8 load.
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define amdgpu_kernel void @load_keep_base_alignment_missing_align(ptr addrspace(1) %out) {
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; CHECK-LABEL: @load_keep_base_alignment_missing_align(
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; CHECK-NEXT: [[PTR0:%.*]] = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 11
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; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr addrspace(3) [[PTR0]], align 4
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; CHECK-NEXT: [[VAL01:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
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; CHECK-NEXT: [[VAL12:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
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; CHECK-NEXT: [[ADD:%.*]] = fadd float [[VAL01]], [[VAL12]]
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; CHECK-NEXT: store float [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 4
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; CHECK-NEXT: ret void
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;
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%ptr0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 11
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%val0 = load float, ptr addrspace(3) %ptr0
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%ptr1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 12
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%val1 = load float, ptr addrspace(3) %ptr1
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%add = fadd float %val0, %val1
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store float %add, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @store_keep_base_alignment_missing_align() {
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; CHECK-LABEL: @store_keep_base_alignment_missing_align(
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; CHECK-NEXT: [[ARRAYIDX0:%.*]] = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 1
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; CHECK-NEXT: store <2 x float> zeroinitializer, ptr addrspace(3) [[ARRAYIDX0]], align 4
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; CHECK-NEXT: ret void
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;
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%arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 1
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%arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 2
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store float 0.0, ptr addrspace(3) %arrayidx0
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store float 0.0, ptr addrspace(3) %arrayidx1
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ret void
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}
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