a57847232f
The tests in this directory all depend on the AMDGPU target being present so we can let opt infer the data layout. Reviewed By: arsenm Pull Request: https://github.com/llvm/llvm-project/pull/137924
89 lines
4.6 KiB
LLVM
89 lines
4.6 KiB
LLVM
; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer,dce -S -o - %s | FileCheck %s
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define void @base_case(i1 %cnd, ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %out) {
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; CHECK-LABEL: @base_case
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; CHECK: load <3 x i32>
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entry:
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%gep1 = getelementptr inbounds i32, ptr addrspace(1) %a, i64 1
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%gep2 = getelementptr inbounds i32, ptr addrspace(1) %a, i64 2
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%gep4 = getelementptr inbounds i32, ptr addrspace(1) %b, i64 1
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%gep5 = getelementptr inbounds i32, ptr addrspace(1) %b, i64 2
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%selected = select i1 %cnd, ptr addrspace(1) %a, ptr addrspace(1) %b
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%selected14 = select i1 %cnd, ptr addrspace(1) %gep1, ptr addrspace(1) %gep4
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%selected25 = select i1 %cnd, ptr addrspace(1) %gep2, ptr addrspace(1) %gep5
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%val0 = load i32, ptr addrspace(1) %selected, align 4
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%val1 = load i32, ptr addrspace(1) %selected14, align 4
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%val2 = load i32, ptr addrspace(1) %selected25, align 4
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%t0 = insertelement <3 x i32> undef, i32 %val0, i32 0
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%t1 = insertelement <3 x i32> %t0, i32 %val1, i32 1
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%t2 = insertelement <3 x i32> %t1, i32 %val2, i32 2
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store <3 x i32> %t2, ptr addrspace(1) %out
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ret void
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}
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define void @scev_targeting_complex_case(i1 %cnd, ptr addrspace(1) %a, ptr addrspace(1) %b, i32 %base, ptr addrspace(1) %out) {
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; CHECK-LABEL: @scev_targeting_complex_case
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; CHECK: load <2 x i32>
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entry:
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%base.x4 = shl i32 %base, 2
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%base.x4.p1 = add i32 %base.x4, 1
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%base.x4.p2 = add i32 %base.x4, 2
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%base.x4.p3 = add i32 %base.x4, 3
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%zext.x4 = zext i32 %base.x4 to i64
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%zext.x4.p1 = zext i32 %base.x4.p1 to i64
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%zext.x4.p2 = zext i32 %base.x4.p2 to i64
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%zext.x4.p3 = zext i32 %base.x4.p3 to i64
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%base.x16 = mul i64 %zext.x4, 4
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%base.x16.p4 = shl i64 %zext.x4.p1, 2
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%base.x16.p8 = shl i64 %zext.x4.p2, 2
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%base.x16.p12 = mul i64 %zext.x4.p3, 4
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%gep.a.base.x16 = getelementptr inbounds i8, ptr addrspace(1) %a, i64 %base.x16
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%gep.b.base.x16.p4 = getelementptr inbounds i8, ptr addrspace(1) %b, i64 %base.x16.p4
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%gep.a.base.x16.p8 = getelementptr inbounds i8, ptr addrspace(1) %a, i64 %base.x16.p8
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%gep.b.base.x16.p12 = getelementptr inbounds i8, ptr addrspace(1) %b, i64 %base.x16.p12
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%selected.base.x16.p0.or.4 = select i1 %cnd, ptr addrspace(1) %gep.a.base.x16, ptr addrspace(1) %gep.b.base.x16.p4
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%gep.selected.base.x16.p8.or.12 = select i1 %cnd, ptr addrspace(1) %gep.a.base.x16.p8, ptr addrspace(1) %gep.b.base.x16.p12
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%selected.base.x16.p40.or.44 = getelementptr inbounds i32, ptr addrspace(1) %selected.base.x16.p0.or.4, i64 10
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%selected.base.x16.p44.or.48 = getelementptr inbounds i32, ptr addrspace(1) %gep.selected.base.x16.p8.or.12, i64 9
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%val0 = load i32, ptr addrspace(1) %selected.base.x16.p40.or.44, align 4
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%val1 = load i32, ptr addrspace(1) %selected.base.x16.p44.or.48, align 4
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%t0 = insertelement <2 x i32> undef, i32 %val0, i32 0
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%t1 = insertelement <2 x i32> %t0, i32 %val1, i32 1
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store <2 x i32> %t1, ptr addrspace(1) %out
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ret void
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}
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define void @nested_selects(i1 %cnd0, i1 %cnd1, ptr addrspace(1) %a, ptr addrspace(1) %b, i32 %base, ptr addrspace(1) %out) {
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; CHECK-LABEL: @nested_selects
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; CHECK: load <2 x i32>
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entry:
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%base.p1 = add nsw i32 %base, 1
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%base.p2 = add i32 %base, 2
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%base.p3 = add nsw i32 %base, 3
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%base.x4 = mul i32 %base, 4
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%base.x4.p5 = add i32 %base.x4, 5
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%base.x4.p6 = add i32 %base.x4, 6
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%sext = sext i32 %base to i64
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%sext.p1 = sext i32 %base.p1 to i64
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%sext.p2 = sext i32 %base.p2 to i64
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%sext.p3 = sext i32 %base.p3 to i64
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%sext.x4.p5 = sext i32 %base.x4.p5 to i64
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%sext.x4.p6 = sext i32 %base.x4.p6 to i64
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%gep.a.base = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %sext
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%gep.a.base.p1 = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %sext.p1
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%gep.a.base.p2 = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %sext.p2
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%gep.a.base.p3 = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %sext.p3
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%gep.b.base.x4.p5 = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %sext.x4.p5
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%gep.b.base.x4.p6 = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %sext.x4.p6
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%selected.1.L = select i1 %cnd1, ptr addrspace(1) %gep.a.base.p2, ptr addrspace(1) %gep.b.base.x4.p5
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%selected.1.R = select i1 %cnd1, ptr addrspace(1) %gep.a.base.p3, ptr addrspace(1) %gep.b.base.x4.p6
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%selected.0.L = select i1 %cnd0, ptr addrspace(1) %gep.a.base, ptr addrspace(1) %selected.1.L
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%selected.0.R = select i1 %cnd0, ptr addrspace(1) %gep.a.base.p1, ptr addrspace(1) %selected.1.R
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%val0 = load i32, ptr addrspace(1) %selected.0.L, align 4
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%val1 = load i32, ptr addrspace(1) %selected.0.R, align 4
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%t0 = insertelement <2 x i32> undef, i32 %val0, i32 0
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%t1 = insertelement <2 x i32> %t0, i32 %val1, i32 1
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store <2 x i32> %t1, ptr addrspace(1) %out
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ret void
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}
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