Matt Arsenault 01d97dfde1 AMDGPU/GlobalISel: Regenerate test checks

2021-12-21 10:57:46 -05:00

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AArch64

[AArch64][SVE] Lower shuffles to permute instructions: zip1/2, uzp1/2, trn1/2

2021-12-21 18:39:09 +08:00

AMDGPU

AMDGPU/GlobalISel: Regenerate test checks

2021-12-21 10:57:46 -05:00

ARC

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ARM

[ARM] Add AddrModeT2_i8neg addressing mode support for frame lowering.

2021-12-14 12:49:27 +00:00

AVR

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BPF

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CSKY

[CSKY] Complete codegen of basic arithmetic and load/store operations

2021-12-09 11:40:20 +08:00

Generic

[NFC][regalloc] Introduce the RegAllocEvictionAdvisorAnalysis

2021-12-16 17:56:46 -08:00

Hexagon

Reapply [xray] add support for hexagon

2021-12-10 05:32:28 -08:00

Inputs

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Lanai

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M68k

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Mips

[MIPS] Allow i1 values for 'r' constraint in inline-asm

2021-12-14 01:19:34 +03:00

MIR

AMDGPU: Enable fixed function ABI by default

2021-12-04 10:49:18 -05:00

MLRegalloc

[NFC][regalloc] Introduce the RegAllocEvictionAdvisorAnalysis

2021-12-16 17:56:46 -08:00

MSP430

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NVPTX

[NVPTX] Auto-generate tests for sufrace and texture instructions

2021-12-07 15:27:51 +03:00

PowerPC

[NFC][regalloc] Introduce the RegAllocEvictionAdvisorAnalysis

2021-12-16 17:56:46 -08:00

RISCV

[RISCV] Precommit tests for override hasAndNotCompare.

2021-12-21 14:24:07 +08:00

SPARC

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SystemZ

[z/OS] Implement prologue and epilogue generation for z/OS target.

2021-12-16 09:04:05 -05:00

Thumb

[clang][ARM] PACBTI-M assembly support

2021-11-30 09:28:18 +00:00

Thumb2

[ARM] Fold away CMP/CSINC from CMOV

2021-12-19 21:53:50 +00:00

VE

[VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests

2021-12-21 09:15:31 +01:00

WebAssembly

[WebAssembly] Add simd-vector-trunc.ll test missing from 2a4a229

2021-12-15 09:22:40 -08:00

WinCFGuard

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WinEH

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X86

[X86] LowerRotate - enable vXi32 splat handling

2021-12-21 11:19:23 +00:00

XCore

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