Sanjay Patel 33a448f935 [DAGCombiner] don't try to extract a fraction of a vector binop and crash (PR39893) ...

Because we're potentially peeking through a bitcast in this transform,
we need to use overall bitwidths rather than number of elements to
determine when it's safe to proceed.

Should fix:
https://bugs.llvm.org/show_bug.cgi?id=39893

llvm-svn: 348383

2018-12-05 17:10:30 +00:00

..

CMakeLists.txt

…

DAGCombiner.cpp

[DAGCombiner] don't try to extract a fraction of a vector binop and crash (PR39893)

2018-12-05 17:10:30 +00:00

FastISel.cpp

Add support for llvm.is.constant intrinsic (PR4898)

2018-11-07 15:24:12 +00:00

FunctionLoweringInfo.cpp

AMDGPU: Fix various issues around the VirtReg2Value mapping

2018-11-30 22:55:29 +00:00

InstrEmitter.cpp

[ARM] Make InstrEmitter mark CPSR defs dead for Thumb1.

2018-10-26 19:32:24 +00:00

InstrEmitter.h

…

LegalizeDAG.cpp

[SelectionDAG] Initial support for FSHL/FSHR funnel shift opcodes (PR39467)

2018-12-05 11:12:12 +00:00

LegalizeFloatTypes.cpp

[NFC] Rename minnan and maxnan to minimum and maximum

2018-10-24 22:49:55 +00:00

LegalizeIntegerTypes.cpp

[SelectionDAG] Support result type promotion for FLT_ROUNDS_

2018-11-30 13:18:33 +00:00

LegalizeTypes.cpp

[DAG] Don't map a TableId to itself in the ReplacedValues map

2018-06-20 16:06:09 +00:00

LegalizeTypes.h

[SelectionDAG] Support result type promotion for FLT_ROUNDS_

2018-11-30 13:18:33 +00:00

LegalizeTypesGeneric.cpp

[LegalizeTypes] Fix bad indentation. NFC

2018-09-23 21:17:55 +00:00

LegalizeVectorOps.cpp

[SelectionDAG] Initial support for FSHL/FSHR funnel shift opcodes (PR39467)

2018-12-05 11:12:12 +00:00

LegalizeVectorTypes.cpp

[LegalizeVectorTypes][X86][ARM][AArch64][PowerPC] Don't use SplitVecOp_TruncateHelper for FP_TO_SINT/UINT.

2018-11-26 21:12:39 +00:00

LLVMBuild.txt

…

ResourcePriorityQueue.cpp

…

ScheduleDAGFast.cpp

ScheduleDAG: Cleanup dumping code; NFC

2018-09-19 00:23:35 +00:00

ScheduleDAGRRList.cpp

ScheduleDAG: Cleanup dumping code; NFC

2018-09-19 00:23:35 +00:00

ScheduleDAGSDNodes.cpp

llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)

2018-09-27 02:13:45 +00:00

ScheduleDAGSDNodes.h

ScheduleDAG: Cleanup dumping code; NFC

2018-09-19 00:23:35 +00:00

ScheduleDAGVLIW.cpp

ScheduleDAG: Cleanup dumping code; NFC

2018-09-19 00:23:35 +00:00

SDNodeDbgValue.h

SelectionDAG: Add compact SDDbgValue representation to -dag-dump-verbose output

2018-09-14 17:08:02 +00:00

SelectionDAG.cpp

[SelectionDAG] Split very large token factors for loads into 64k chunks.

2018-12-05 00:41:30 +00:00

SelectionDAGAddressAnalysis.cpp

[SelectionDAG] Teach BaseIndexOffset::match to unwrap the base after looking through an add/or

2018-11-26 20:16:33 +00:00

SelectionDAGBuilder.cpp

[SelectionDAG] Initial support for FSHL/FSHR funnel shift opcodes (PR39467)

2018-12-05 11:12:12 +00:00

SelectionDAGBuilder.h

[IR] Add a dedicated FNeg IR Instruction

2018-11-13 18:15:47 +00:00

SelectionDAGDumper.cpp

[SelectionDAG] Initial support for FSHL/FSHR funnel shift opcodes (PR39467)

2018-12-05 11:12:12 +00:00

SelectionDAGISel.cpp

TableGen/ISel: Allow PatFrag predicate code to access captured operands

2018-11-30 14:15:13 +00:00

SelectionDAGPrinter.cpp

Rename DEBUG macro to LLVM_DEBUG.

2018-05-14 12:53:11 +00:00

SelectionDAGTargetInfo.cpp

…

StatepointLowering.cpp

[CodeGen] Prefer static frame index for STATEPOINT liveness args

2018-11-30 16:22:41 +00:00

StatepointLowering.h

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TargetLowering.cpp

[TargetLowering] Remove ISD::ANY_EXTEND/ANY_EXTEND_VECTOR_INREG opcodes from SimplifyDemandedVectorElts

2018-12-05 12:20:05 +00:00