49045c6a0d
Reapply r346374 with the fixes for modules build. Original summary: This change implements assembler parser, code emitter, ELF object writer and disassembler for the MSP430 ISA. Also, more instruction forms are added to the target description. Patch by Michael Skvortsov! llvm-svn: 346948
30 lines
867 B
LLVM
30 lines
867 B
LLVM
; RUN: llc -O0 -disable-fp-elim < %s | FileCheck %s
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target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
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target triple = "msp430---elf"
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define void @fp() nounwind {
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entry:
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; CHECK-LABEL: fp:
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; CHECK: push r4
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; CHECK: mov r1, r4
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; CHECK: sub #2, r1
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%i = alloca i16, align 2
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; CHECK: clr -2(r4)
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store i16 0, i16* %i, align 2
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; CHECK: pop r4
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ret void
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}
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; Due to FPB not being marked as reserved, the register allocator used to select
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; r4 as the register for the "r" constraint below. This test verifies that this
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; does not happen anymore. Note that the only reason an ISR is used here is that
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; the register allocator selects r4 first instead of fifth in a normal function.
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define msp430_intrcc void @fpb_alloced() #0 {
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; CHECK-LABEL: fpb_alloced:
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; CHECK-NOT: mov.b #0, r4
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; CHECK: nop
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call void asm sideeffect "nop", "r"(i8 0)
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ret void
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}
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