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0362a29905ab8d68a8eb48741840a514b66552f8
clang-p2996/llvm/test/CodeGen/RISCV
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Craig Topper 43d0bb571b [RISCV] Add more srli+slli.uw tests cases for #100936. NFC
2024-07-28 20:13:55 -07:00
..
GlobalISel
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
intrinsics
…
rv64-legal-i32
[LegalizeDAG] Optimize CodeGen for ISD::CTLZ_ZERO_UNDEF (#83039)
2024-07-08 14:01:32 +01:00
rvv
[RISCV] Add FMA support to combineOp_VLToVWOp_VL. (#100454)
2024-07-26 09:12:40 -07:00
add-before-shl.ll
…
add-imm.ll
…
addc-adde-sube-subc.ll
…
addcarry.ll
…
addimm-mulimm.ll
[RISCV] Use RISCVISD::SHL_ADD in transformAddShlImm (#89832)
2024-05-13 09:48:46 -07:00
addrspacecast.ll
…
aext-to-sext.ll
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aext.ll
…
align-loops.ll
…
align.ll
…
alloca.ll
…
allow-check.ll
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alu8.ll
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alu16.ll
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alu32.ll
…
alu64.ll
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
2024-04-29 13:08:52 +02:00
analyze-branch.ll
…
and-add-lsr.ll
…
and.ll
…
arith-with-overflow.ll
…
atomic-cmpxchg-branch-on-result.ll
[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)
2024-07-23 08:06:15 +01:00
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll
[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)
2024-07-23 08:06:15 +01:00
atomic-fence.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
atomic-load-store.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
atomic-rmw-discard.ll
…
atomic-rmw-sub.ll
…
atomic-rmw.ll
[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)
2024-07-23 08:06:15 +01:00
atomic-signext.ll
[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)
2024-07-23 08:06:15 +01:00
atomicrmw-uinc-udec-wrap.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
attributes-module-flag.ll
[RISCV] Make M imply Zmmul (#95070)
2024-06-21 11:11:10 +08:00
attributes.ll
[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)
2024-07-23 08:06:15 +01:00
avgceils.ll
[RISCV] Add scalar type test coverage for ISD::AVG nodes
2024-06-15 16:15:50 +01:00
avgceilu.ll
[RISCV] Add scalar type test coverage for ISD::AVG nodes
2024-06-15 16:15:50 +01:00
avgfloors.ll
[RISCV] Add scalar type test coverage for ISD::AVG nodes
2024-06-15 16:15:50 +01:00
avgflooru.ll
Revert "[DAG] Reducing instructions by better legalization handling of AVGFLOORU for illegal data types (#99913)"
2024-07-27 18:35:44 -07:00
bf16-promote.ll
…
bfloat-arith.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-br-fcmp.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-convert.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-fcmp.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-frem.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-imm.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-isnan.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-mem.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-select-fcmp.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-select-icmp.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat.ll
…
bitextract-mac.ll
…
bitreverse-shift.ll
[DAG] Fold bitreverse(shl/srl(bitreverse(x),y)) -> srl/shl(x,y) (#89897)
2024-05-06 11:13:05 +01:00
bittest.ll
…
blockaddress.ll
…
branch_zero.ll
…
branch-on-zero.ll
…
branch-opt.ll
…
branch-opt.mir
…
branch-relaxation.ll
…
branch.ll
…
bswap-bitreverse.ll
…
bswap-shift.ll
…
byval.ll
…
callee-saved-fpr32s.ll
…
callee-saved-fpr64s.ll
…
callee-saved-gprs.ll
…
calling-conv-half.ll
…
calling-conv-ilp32-ilp32f-common.ll
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calling-conv-ilp32-ilp32f-ilp32d-common.ll
…
calling-conv-ilp32.ll
…
calling-conv-ilp32d.ll
…
calling-conv-ilp32e.ll
…
calling-conv-ilp32f-ilp32d-common.ll
…
calling-conv-lp64-lp64f-common.ll
…
calling-conv-lp64-lp64f-lp64d-common.ll
[mi-sched] Suppress register pressure with i64. (#88256)
2024-04-15 13:11:45 +08:00
calling-conv-lp64.ll
…
calling-conv-lp64e.ll
…
calling-conv-rv32f-ilp32.ll
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calling-conv-rv32f-ilp32e.ll
…
calling-conv-sext-zext.ll
…
calling-conv-vector-float.ll
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calling-conv-vector-on-stack.ll
…
calls.ll
…
clear-cache.ll
[RISCV] Lower llvm.clear_cache to __riscv_flush_icache for glibc targets (#93481)
2024-06-20 07:27:07 +02:00
cm_mvas_mvsa.ll
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cm_mvas_mvsa.mir
…
cmov-branch-opt.ll
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cmp-bool.ll
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codemodel-lowering.ll
…
compress-double.ll
…
compress-float.ll
…
compress-inline-asm.ll
…
compress-opt-branch.ll
[RISCV] Add Zca predicate to BrccCompressOpt patterns used for MinSize.
2024-04-05 12:39:39 -07:00
compress-opt-select.ll
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compress.ll
…
condbinops.ll
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condops.ll
[RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891)
2024-07-27 17:26:32 -07:00
convert-highly-predictable-select-to-branch.ll
[RISCV] Add FeaturePredictableSelectIsExpensive
2024-07-05 11:29:42 +08:00
copy-frameindex.mir
…
copyprop.ll
…
copysign-casts.ll
…
ctlz-cttz-ctpop.ll
[LegalizeDAG] Optimize CodeGen for ISD::CTLZ_ZERO_UNDEF (#83039)
2024-07-08 14:01:32 +01:00
ctz_zero_return_test.ll
[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352)
2024-05-28 15:05:23 -07:00
disable-tail-calls.ll
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disjoint.ll
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div_minsize.ll
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div-by-constant.ll
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div-pow2.ll
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div.ll
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double_reduct.ll
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double-arith-strict.ll
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double-arith.ll
[RISCV][ISel] Fold FSGNJX idioms (#100718)
2024-07-27 12:51:58 +08:00
double-bitmanip-dagcombines.ll
DAG: Call SimplifyDemandedBits on fcopysign sign value (#97151)
2024-07-01 12:19:17 +02:00
double-br-fcmp.ll
…
double-calling-conv.ll
…
double-convert-strict.ll
…
double-convert.ll
[DAGCombiner] Push freeze through SETCC and SELECT_CC (#64718)
2024-07-22 16:01:59 +02:00
double-fcmp-strict.ll
…
double-fcmp.ll
…
double-frem.ll
…
double-imm.ll
…
double-intrinsics-strict.ll
[clang] Reland Add tanf16 builtin and support for tan constrained intrinsic (#94559)
2024-06-10 20:46:26 -04:00
double-intrinsics.ll
Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"
2024-06-21 08:34:04 +02:00
double-isnan.ll
…
double-maximum-minimum.ll
…
double-mem.ll
…
double-previous-failure.ll
…
double-round-conv-sat.ll
[DAGCombiner] Push freeze through SETCC and SELECT_CC (#64718)
2024-07-22 16:01:59 +02:00
double-round-conv.ll
…
double-select-fcmp.ll
…
double-select-icmp.ll
…
double-stack-spill-restore.ll
…
double-zfa.ll
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dso_local_equivalent.ll
…
dwarf-eh.ll
…
early-clobber-tied-def-subreg-liveness.ll
[CodeGen] Remove target SubRegLiveness flags (#95437)
2024-06-14 08:51:56 +01:00
eh-dwarf-cfa.ll
…
elf-preemption.ll
…
emutls.ll
…
exception-pointer-register.ll
…
fastcc-float.ll
…
fastcc-int.ll
[RISCV] Remove x7 from fastcc list. (#96729)
2024-07-17 08:37:55 +08:00
fastcc-without-f-reg.ll
[RISCV] Remove x7 from fastcc list. (#96729)
2024-07-17 08:37:55 +08:00
fixups-diff.ll
[MC] Rename temporary symbols of empty name to ".L0 " (#89693)
2024-04-26 08:30:27 -07:00
fli-licm.ll
…
float-arith-strict.ll
…
float-arith.ll
[RISCV][ISel] Fold FSGNJX idioms (#100718)
2024-07-27 12:51:58 +08:00
float-bit-preserving-dagcombines.ll
…
float-bitmanip-dagcombines.ll
DAG: Call SimplifyDemandedBits on fcopysign sign value (#97151)
2024-07-01 12:19:17 +02:00
float-br-fcmp.ll
…
float-convert-strict.ll
…
float-convert.ll
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
2024-04-29 13:08:52 +02:00
float-fcmp-strict.ll
…
float-fcmp.ll
…
float-frem.ll
…
float-imm.ll
…
float-intrinsics-strict.ll
[clang] Reland Add tanf16 builtin and support for tan constrained intrinsic (#94559)
2024-06-10 20:46:26 -04:00
float-intrinsics.ll
Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"
2024-06-21 08:34:04 +02:00
float-isnan.ll
…
float-maximum-minimum.ll
…
float-mem.ll
…
float-round-conv-sat.ll
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
2024-04-29 13:08:52 +02:00
float-round-conv.ll
…
float-select-fcmp.ll
…
float-select-icmp.ll
…
float-select-verify.ll
…
float-zfa.ll
…
flt-rounds.ll
…
fmax-fmin.ll
…
fold-addi-loadstore.ll
[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352)
2024-05-28 15:05:23 -07:00
fold-binop-into-select-return-constant.ll
[RISCV] Add a check in lowerSELECT after foldBinOpIntoSelectIfProfitable (#97391)
2024-07-05 10:55:36 +08:00
fold-binop-into-select.ll
…
forced-atomics.ll
Reapply "[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)" (#90267)
2024-07-08 13:35:36 -07:00
fp16-promote.ll
…
fp128.ll
…
fpclamptosat.ll
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
2024-04-29 13:08:52 +02:00
fpenv.ll
…
frame-info.ll
…
frame.ll
…
frameaddr-returnaddr.ll
…
frm-dependency.ll
…
get-register-invalid.ll
…
get-register-noreserve.ll
…
get-register-reserve.ll
…
get-setcc-result-type.ll
…
ghccc-nest.ll
…
ghccc-rv32.ll
…
ghccc-rv64.ll
…
ghccc-without-f-reg.ll
…
global-merge-minsize-smalldata-nonzero.ll
[GlobalMerge] Add MinSize feature to the GlobalMerge Pass. (#93686)
2024-06-03 09:10:56 -04:00
global-merge-minsize-smalldata-zero.ll
[GlobalMerge] Add MinSize feature to the GlobalMerge Pass. (#93686)
2024-06-03 09:10:56 -04:00
global-merge-minsize.ll
[GlobalMerge] Add MinSize feature to the GlobalMerge Pass. (#93686)
2024-06-03 09:10:56 -04:00
global-merge-offset.ll
…
global-merge.ll
…
graalcc.ll
…
half-arith-strict.ll
…
half-arith.ll
[RISCV][ISel] Fold FSGNJX idioms (#100718)
2024-07-27 12:51:58 +08:00
half-bitmanip-dagcombines.ll
…
half-br-fcmp.ll
…
half-convert-strict.ll
…
half-convert.ll
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
2024-04-29 13:08:52 +02:00
half-fcmp-strict.ll
…
half-fcmp.ll
…
half-frem.ll
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half-imm.ll
…
half-intrinsics.ll
[CodeGen] Support vectors across all backends (#95518)
2024-06-14 17:18:20 -04:00
half-isnan.ll
…
half-maximum-minimum.ll
…
half-mem.ll
…
half-round-conv-sat.ll
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
2024-04-29 13:08:52 +02:00
half-round-conv.ll
…
half-select-fcmp.ll
…
half-select-icmp.ll
…
half-zfa-fli.ll
…
half-zfa.ll
…
hoist-global-addr-base.ll
…
hwasan-check-memaccess.ll
…
i32-icmp.ll
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i64-icmp.ll
…
iabs.ll
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
2024-04-29 13:08:52 +02:00
idiv_large.ll
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imm-cse.ll
…
imm.ll
[RISCV] Improve constant materialisation for stores of i8 negative constants (#92131)
2024-05-14 19:08:04 +01:00
indirectbr.ll
…
init-array.ll
…
inline-asm-abi-names.ll
…
inline-asm-clobbers.ll
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inline-asm-d-abi-names.ll
…
inline-asm-d-constraint-f.ll
…
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll
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inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
…
inline-asm-mem-constraint.ll
[RISCV] Don't crash in RISCVMergeBaseOffset if INLINE_ASM uses address register in a non-memory constraint. (#100790)
2024-07-26 17:11:01 -07:00
inline-asm-s-constraint-error.ll
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inline-asm-s-constraint.ll
…
inline-asm-zfh-constraint-f.ll
…
inline-asm.ll
…
inline-option-directive.ll
…
interrupt-attr-args-error.ll
…
interrupt-attr-callee.ll
…
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll
[RISCV] Remove interrupt handler special case from RISCVFrameLowering::determineCalleeSaves. (#88069)
2024-04-10 10:28:54 -07:00
interrupt-attr-ret-error.ll
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interrupt-attr.ll
[RISCV] Remove interrupt handler special case from RISCVFrameLowering::determineCalleeSaves. (#88069)
2024-04-10 10:28:54 -07:00
intrinsic-cttz-elts-vscale.ll
[RISCV] Support postRA vsetvl insertion pass (#70549)
2024-05-21 14:42:55 +08:00
intrinsic-cttz-elts.ll
[RISCV] Provide a more efficient lowering for experimental.cttz.elts. (#88552)
2024-04-15 18:38:54 -07:00
isel-optnone.ll
…
jumptable-swguarded.ll
[RISCV] Use software guarded branch for indirect jump table branch. (#66762)
2024-05-14 14:44:25 +08:00
jumptable.ll
…
kcfi-isel-mir.ll
…
kcfi-mir.ll
…
kcfi-patchable-function-prefix.ll
…
kcfi.ll
…
lack-of-signed-truncation-check.ll
…
large-stack.ll
…
legalize-fneg.ll
…
libcall-tail-calls.ll
…
lit.local.cfg
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live-sp.mir
…
llvm.exp10.ll
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llvm.frexp.ll
…
load-setcc-combine.ll
…
local-stack-slot-allocation.ll
[RISCV] Don't exlude the frame pointer from the callee saved registers in RISCVRegisterInfo::needsFrameBaseReg.
2024-05-13 12:58:30 -07:00
loop-strength-reduce-add-cheaper-than-mul.ll
…
loop-strength-reduce-loop-invar.ll
[RISCV][LSR] Account for temporary register for base addition (#92296)
2024-05-22 13:38:39 -07:00
lsr-legaladdimm.ll
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machine-combiner-mir.ll
…
machine-combiner-strategies.ll
…
machine-combiner.ll
…
machine-combiner.mir
…
machine-cp.mir
…
machine-cse.ll
…
machine-outliner-and-machine-copy-propagation.ll
…
machine-outliner-cfi.mir
…
machine-outliner-patchable.ll
…
machine-outliner-position.mir
…
machine-outliner-throw.ll
…
machine-sink-load-immediate.ll
[MachineSink] Fix missing sinks along critical edges (#97618)
2024-07-09 10:48:22 -07:00
machinelicm-address-pseudos.ll
…
machinelicm-constant-phys-reg.ll
[MachineLICM] Hoist copies of constant physical register (#93285)
2024-05-29 14:10:01 +08:00
machineoutliner-jumptable.mir
…
machineoutliner-pcrel-lo.mir
[MachineOutliner] Leaf Descendants (#90275)
2024-06-18 07:13:05 -07:00
machineoutliner.mir
…
MachineSink-implicit-x0.mir
…
macro-fusion-lui-addi.ll
…
macro-fusions.mir
…
make-compressible-for-store-address.mir
…
make-compressible-rv64.mir
…
make-compressible-zbc.mir
…
make-compressible.mir
…
mem64.ll
…
mem.ll
…
memcpy-inline.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
memcpy.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
memset-inline.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
min-max.ll
…
mir-target-flags.ll
…
misched-load-clustering.ll
…
misched-postra-direction.mir
…
miss-sp-restore-eh.ll
…
module-elf-flags.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
module-target-abi2.ll
…
module-target-abi3.ll
…
module-target-abi.ll
…
mul.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
musttail-call.ll
…
narrow-shl-cst.ll
…
neg-abs.ll
…
nest-register.ll
…
nomerge.ll
…
nontemporal-scalable.ll
…
nontemporal.ll
…
O0-pipeline.ll
[RISCV] Teach RISCVInsertVSETVLI to work without LiveIntervals
2024-06-17 12:05:43 -07:00
O3-pipeline.ll
[RISCV] Update RISCVVectorPeephole pass name
2024-07-26 10:33:38 +08:00
opt-w-instrs.mir
…
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax-relocation.ll
…
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll
…
or-is-add.ll
…
out-of-reach-emergency-slot.mir
…
overflow-intrinsic-optimizations.ll
…
overflow-intrinsics.ll
…
patchable-function-entry.ll
…
pei-crash.ll
…
pic-models.ll
…
pr40333.ll
…
pr51206.ll
…
pr53662.mir
…
pr55201.ll
…
pr56110.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
pr56457.ll
…
pr58025.ll
…
pr58286.ll
…
pr58511.ll
…
pr63365.ll
…
pr63816.ll
…
pr64503.ll
…
pr64645.ll
…
pr64772.ll
…
pr64935.ll
…
pr65025.ll
…
pr66603.ll
…
pr68855.ll
…
pr69586.ll
[RISCV] Support postRA vsetvl insertion pass (#70549)
2024-05-21 14:42:55 +08:00
pr80052.mir
…
pr84200.ll
…
pr84653_pr85190.ll
[DAGCombiner] Freeze maybe poison operands when folding select to logic (#84924)
2024-07-22 17:19:46 +02:00
pr88365.ll
[LLVM] [MC] Update frame layout & CFI generation to handle frames larger than 2gb (#99263)
2024-07-23 09:43:30 -07:00
pr90652.ll
[RISCV][ISel] Fix types in tryFoldSelectIntoOp (#90659)
2024-05-01 06:51:36 +08:00
pr90730.ll
[RISCV][ISel] Allow opaque constants in hasAndNotCompare (#92926)
2024-05-22 00:48:26 +08:00
pr92193.ll
[DAGCombiner] Mark vectors as not AllAddOne/AllSubOne on type mismatch (#92195)
2024-05-15 12:39:28 -07:00
pr94145.ll
[DAG] canCreateUndefOrPoison - fix missing argument typo
2024-06-02 10:34:48 +01:00
pr94265.ll
[SelectionDAG][RISCV] Fix break of vnsrl pattern in issue #94265 (#95563)
2024-07-14 12:09:37 +01:00
pr95271.ll
[DAG] combineShiftToAVG - only create new types before LegalTypes
2024-06-12 18:49:49 +01:00
pr95284.ll
[DAG] combineShiftToAVG - don't create avgfloor with scalar constant operands unless legal.
2024-06-13 12:37:43 +01:00
pr96366.ll
[SDAG] Intersect poison-generating flags after CSE (#97434)
2024-07-03 20:32:46 +08:00
pr97304.ll
[RISCV] Copy call frame size when splitting basic block in emitSelectPseudo. (#99823)
2024-07-22 09:21:01 -07:00
prefer-w-inst.ll
[RISCV] Generate more W instructons
2024-04-16 15:37:31 +08:00
prefer-w-inst.mir
[RISCV] Generate more W instructons
2024-04-16 15:37:31 +08:00
prefetch.ll
…
prolog-epilogue.ll
[RISCV] Exploit sh3add/sh2add for stack offsets by shifted 12-bit constants (#87950)
2024-04-08 14:53:21 -07:00
push-pop-opt-crash.ll
…
push-pop-popret.ll
[RISCV] Add X27 to SavedRegs when X26 is in SavedRegs for cm.push/pop (#92067)
2024-05-14 08:06:10 -07:00
readcyclecounter.ll
…
readsteadycounter.ll
…
reduce-unnecessary-extension.ll
…
reduction-formation.ll
…
regalloc-last-chance-recoloring-failure.ll
[CodeGen] Remove target SubRegLiveness flags (#95437)
2024-06-14 08:51:56 +01:00
relax-per-target-feature.ll
…
rem.ll
…
remat.ll
…
repeated-fp-divisors.ll
…
reserved-reg-errors.ll
…
reserved-regs.ll
…
riscv-codegenprepare-asm.ll
…
riscv-codegenprepare.ll
…
riscv-func-target-feature.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
riscv-shifted-extend.ll
…
rotl-rotr.ll
…
rv32-fuchsia.ll
…
rv32e.ll
…
rv32i-rv64i-float-double.ll
…
rv32i-rv64i-half.ll
…
rv32xtheadba.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
rv32xtheadbb.ll
[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352)
2024-05-28 15:05:23 -07:00
rv32xtheadbs.ll
…
rv32zba.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
rv32zbb-intrinsic.ll
…
rv32zbb-zbkb.ll
…
rv32zbb.ll
[RISCV] Add DAG combine to turn (sub (shl X, 8), X) into orc.b (#96680)
2024-06-25 15:55:09 -07:00
rv32zbc-intrinsic.ll
…
rv32zbc-zbkc-intrinsic.ll
…
rv32zbkb-intrinsic.ll
…
rv32zbkb.ll
[RISCV] Support zext.h mnemonic with Zbkb. (#96821)
2024-06-27 09:31:26 -07:00
rv32zbkx-intrinsic.ll
…
rv32zbs.ll
…
rv32zimop-intrinsic.ll
[RISCV] Zimop/Zcmop are ratified
2024-04-08 16:40:02 +08:00
rv32zknd-intrinsic-autoupgrade.ll
…
rv32zknd-intrinsic.ll
…
rv32zkne-intrinsic-autoupgrade.ll
…
rv32zkne-intrinsic.ll
…
rv32zknh-intrinsic.ll
…
rv32zksed-intrinsic-autoupgrade.ll
…
rv32zksed-intrinsic.ll
…
rv32zksh-intrinsic.ll
…
rv64-large-stack.ll
…
rv64-patchpoint.ll
[RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#77337)
2024-04-11 12:19:56 +08:00
rv64-stackmap-frame-setup.ll
…
rv64-stackmap-nops.ll
…
rv64-stackmap.ll
…
rv64-statepoint-call-lowering-x1.ll
[RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#77337)
2024-04-11 12:19:56 +08:00
rv64-statepoint-call-lowering-x2.ll
[RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#77337)
2024-04-11 12:19:56 +08:00
rv64-statepoint-call-lowering.ll
[RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#77337)
2024-04-11 12:19:56 +08:00
rv64-typepromotion.ll
…
rv64d-double-convert-strict.ll
…
rv64d-double-convert.ll
…
rv64e.ll
…
rv64f-float-convert-strict.ll
…
rv64f-float-convert.ll
…
rv64i-complex-float.ll
…
rv64i-demanded-bits.ll
[RISCV][ISel] Eliminate andi rd, rs1, -1 instructions (#89976)
2024-04-25 14:22:14 +08:00
rv64i-double-softfloat.ll
…
rv64i-exhaustive-w-insts.ll
…
rv64i-shift-sext.ll
…
rv64i-single-softfloat.ll
…
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
…
rv64m-exhaustive-w-insts.ll
…
rv64m-w-insts-legalization.ll
…
rv64xtheadba.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
rv64xtheadbb.ll
…
rv64xtheadbs.ll
…
rv64zba.ll
[RISCV] Add more srli+slli.uw tests cases for #100936. NFC
2024-07-28 20:13:55 -07:00
rv64zbb-intrinsic.ll
…
rv64zbb-zbkb.ll
…
rv64zbb.ll
[RISCV] Add DAG combine to turn (sub (shl X, 8), X) into orc.b (#96680)
2024-06-25 15:55:09 -07:00
rv64zbc-intrinsic.ll
…
rv64zbc-zbkc-intrinsic.ll
…
rv64zbkb-intrinsic.ll
…
rv64zbkb.ll
[RISCV] Support zext.h mnemonic with Zbkb. (#96821)
2024-06-27 09:31:26 -07:00
rv64zbkx-intrinsic.ll
…
rv64zbs.ll
…
rv64zfh-half-convert-strict.ll
…
rv64zfh-half-convert.ll
…
rv64zfh-half-intrinsics.ll
…
rv64zfhmin-half-convert-strict.ll
…
rv64zfhmin-half-convert.ll
…
rv64zfhmin-half-intrinsics.ll
…
rv64zimop-intrinsic.ll
[RISCV] Zimop/Zcmop are ratified
2024-04-08 16:40:02 +08:00
rv64zknd-intrinsic.ll
…
rv64zknd-zkne-intrinsic.ll
…
rv64zkne-intrinsic.ll
…
rv64zknh-intrinsic-autoupgrade.ll
…
rv64zknh-intrinsic.ll
…
rv64zksed-intrinsic-autoupgrade2.ll
…
rv64zksed-intrinsic-autoupgrade.ll
…
rv64zksed-intrinsic.ll
…
rv64zksh-intrinsic-autoupgrade.ll
…
rv64zksh-intrinsic.ll
…
rvv-cfi-info.ll
[RISCV][CFI] Emit cfi_offset for every callee-saved vector registers (#100455)
2024-07-29 11:03:07 +08:00
sadd_sat_plus.ll
…
sadd_sat.ll
…
saverestore-scs.ll
…
saverestore.ll
…
scmp.ll
[SelectionDAG] Expand [US]CMP using arithmetic on boolean values instead of selects (#98774)
2024-07-16 20:56:18 +01:00
sdata-limit-0.ll
…
sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
sdiv-pow2-cmov.ll
…
select-and.ll
…
select-bare.ll
…
select-binop-identity.ll
…
select-cc.ll
…
select-const.ll
…
select-constant-xor.ll
…
select-optimize-multiple.ll
…
select-optimize-multiple.mir
[NewPM][CodeGen] Port finalize-isel to new pass manager (#94214)
2024-06-04 09:23:52 +08:00
select-or.ll
…
select-to-and-zext.ll
…
select.ll
[RISC-V][ISel] Remove redundant czero.eqz like 'czero.eqz a0, a0, a0' (#90208)
2024-04-28 13:28:14 +08:00
selectcc-to-shiftand.ll
…
setcc-logic.ll
…
sext-zext-trunc.ll
…
sextw-removal-debug.mir
…
sextw-removal.ll
[SDAG] Improve SimplifyDemandedBits for mul (#90034)
2024-05-22 22:43:10 +08:00
shadowcallstack.ll
…
shift-amount-mod.ll
…
shift-and.ll
…
shift-masked-shamt.ll
…
shifts.ll
…
shl-cttz.ll
[DAGCombine] Transform shl X, cttz(Y) to mul (Y & -Y), X if cttz is unsupported (#85066)
2024-05-29 18:26:54 +08:00
shl-demanded.ll
…
shlimm-addimm.ll
…
short-forward-branch-opt.ll
…
shrinkwrap-jump-table.ll
…
shrinkwrap.ll
…
sifive7-enable-intervals.mir
…
signbit-test.ll
…
signed-truncation-check.ll
…
sink-and-fold-crash.mir
[MachineSink][RISCV] Only call isConstantPhysReg or isIgnorableUse for uses. (#99363)
2024-07-17 13:06:58 -07:00
sink-icmp.ll
…
spill-fill-fold.ll
…
spill-fpr-scalar.ll
[RISCV] Rewrite spill-fpr-scalar.ll test to not use vsetvli. NFC (#91428)
2024-05-08 11:33:05 +08:00
spir-kernel-cc.ll
…
split-offsets.ll
…
split-sp-adjust.ll
…
split-store.ll
…
split-udiv-by-constant.ll
…
split-urem-by-constant.ll
…
srem-lkk.ll
…
srem-seteq-illegal-types.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
srem-vector-lkk.ll
…
srodata.ll
…
ssub_sat_plus.ll
…
ssub_sat.ll
…
stack-folding.ll
…
stack-inst-compress.mir
…
stack-offset.ll
[RISCV] Exploit sh3add/sh2add for stack offsets by shifted 12-bit constants (#87950)
2024-04-08 14:53:21 -07:00
stack-protector-target.ll
[RISCV] Use the thread local stack protector for Android targets (#87672)
2024-05-13 08:52:59 -07:00
stack-realignment-with-variable-sized-objects.ll
…
stack-realignment.ll
…
stack-slot-coloring.mir
…
stack-slot-size.ll
…
stack-store-check.ll
…
subtarget-features-std-ext.ll
…
switch-width.ll
…
tagged-globals.ll
…
tail-calls.ll
[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352)
2024-05-28 15:05:23 -07:00
target-abi-invalid.ll
…
target-abi-valid.ll
…
thread-pointer.ll
…
tls-models.ll
…
tlsdesc-symbol.ll
…
trunc-free.ll
…
typepromotion-overflow.ll
…
uadd_sat_plus.ll
…
uadd_sat.ll
…
ucmp.ll
[SelectionDAG] Expand [US]CMP using arithmetic on boolean values instead of selects (#98774)
2024-07-16 20:56:18 +01:00
umulo-128-legalisation-lowering.ll
…
unaligned-load-store.ll
[RISCV] Improve constant materialisation for stores of i8 negative constants (#92131)
2024-05-14 19:08:04 +01:00
unfold-masked-merge-scalar-variablemask.ll
…
unroll-loop-cse.ll
[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352)
2024-05-28 15:05:23 -07:00
urem-lkk.ll
…
urem-seteq-illegal-types.ll
…
urem-vector-lkk.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
usub_sat_plus.ll
…
usub_sat.ll
…
vararg-ilp32e.ll
…
vararg.ll
…
vector-abi.ll
…
verify-instr.mir
[CodeGen][NewPM] Port MachineVerifier to new pass manager (#98628)
2024-07-15 12:42:44 +08:00
vlenb.ll
[MachineLICM] Hoist copies of constant physical register (#93285)
2024-05-29 14:10:01 +08:00
vscale-demanded-bits.ll
…
wide-mem.ll
…
wide-scalar-shift-by-byte-multiple-legalization.ll
…
wide-scalar-shift-legalization.ll
…
xaluo.ll
[RISCV] Use SHL_ADD in remaining strength reduce cases for MUL (#89789)
2024-04-23 12:40:55 -07:00
xcvalu.ll
[RISCV] Implement Intrinsics Support for XCValu Extension in CV32E40P (#85603)
2024-07-04 01:25:10 +10:00
xcvbi.ll
[RISCV] Codegen support for XCVbi extension (#89719)
2024-05-08 11:22:16 +08:00
xcvbitmanip.ll
…
xcvmac.ll
[RISCV] Implement Intrinsics for XCVmac Extension in CV32E40P (#83112)
2024-07-15 10:25:25 +10:00
xcvmem.ll
[RISCV] Codegen support for XCVmem extension (#76916)
2024-06-07 21:45:49 +08:00
xtheadfmemidx.ll
…
xtheadmac.ll
…
xtheadmemidx.ll
…
xtheadmempair.ll
…
zbb-cmp-combine.ll
…
zcb-regalloc-hints.ll
…
zcmp-additional-stack.ll
…
zcmp-cm-popretz.mir
…
zcmp-cm-push-pop.mir
…
zcmp-prolog-epilog-crash.mir
…
zcmp-with-float.ll
…
zdinx-asm-constraint.ll
…
zdinx-boundary-check.ll
…
zdinx-large-spill.mir
…
zext-with-load-is-free.ll
…
zfbfmin.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
zfh-half-intrinsics-strict.ll
…
zfh-half-intrinsics.ll
…
zfhmin-half-intrinsics-strict.ll
…
zfhmin-half-intrinsics.ll
…
zfhmin-imm.ll
…
zicfilp-indirect-branch.ll
[RISCV] Avoid using x7/t2 for indirect branches which need landing pad. (#68292)
2024-05-02 10:32:40 +08:00
zmmul.ll
…