Matt Arsenault 3a2ef3a634 AMDGPU: Add some baseline cost model tests (#100797)

2024-07-29 12:13:51 +04:00

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AArch64

[SLP] Order clustered load base pointers by ascending offsets (#100653)

2024-07-27 11:18:56 +01:00

AMDGPU

AMDGPU: Add some baseline cost model tests (#100797)

2024-07-29 12:13:51 +04:00

ARM

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NVPTX

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PowerPC

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RISCV

[SLP]Do not trunc bv nodes, if the user is vectorized an requires wider type.

2024-07-19 07:28:04 -07:00

SystemZ

[SLP]Fix PR99899: Use canonical type instead of original vector of ptr.

2024-07-22 13:05:12 -07:00

VE

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WebAssembly

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X86

[SLP]Add external uses cost for the gathered loads.

2024-07-26 11:09:44 -04:00

XCore

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alt-cmp-vectorize.ll

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alternate-non-profitable.ll

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const-bool-logical-or-reduction.ll

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ext-after-phi-node.ll

[SLP]Fix PR90780: insert cast instruction for PHI nodes after all phi nodes.

2024-05-02 06:30:14 -07:00

insertelement-across-zero.ll

[SLP]Fix PR89187: fixx assertion check.

2024-04-18 04:22:25 -07:00

int_sideeffect.ll

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is_fpclass.ll

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orig-btiwidth-les-projected.ll

Revert "[SLP]Improve minbitwidth analysis for trun'ed gather nodes."

2024-07-17 05:51:54 -07:00

phi-not-ordered.ll

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rdar128092379.ll

[llvm][SLPVectorizer] Fix a bad cast assertion (#97621)

2024-07-03 16:25:32 -07:00

reschedule.ll

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revec.ll

[SLP][REVEC] Make Instruction::Call support vector instructions. (#99317)

2024-07-18 20:49:53 +08:00

slp-hr-with-reuse.ll

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slp-max-phi-size.ll

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slp-max-reg-size.ll

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slp-non-pow-2-insertelement.ll

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slp-umax-rdx-matcher-crash.ll

[SLP]Keep the original order in the reductions.

2024-07-09 12:26:42 -04:00

slp-variable-insertelement.ll

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vectorizable-functions-inseltpoison.ll

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vectorizable-functions.ll

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