0ce46a1d43
This patch splits the existing SveVectorBits LangOpt into VScaleMin and
VScaleMax LangOpts such that we can represent such an option. The cc1
option has also been split into -mvscale-{min,max}=<n> options so that the
cc1 arguments better reflect the vscale_range IR attribute.
Differential Revision: https://reviews.llvm.org/D111790
129 lines
6.1 KiB
C++
129 lines
6.1 KiB
C++
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu %s -emit-llvm -o - \
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// RUN: -target-feature +sve -target-feature +bf16 -mvscale-min=1 -mvscale-max=1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-128
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu %s -emit-llvm -o - \
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// RUN: -target-feature +sve -target-feature +bf16 -mvscale-min=2 -mvscale-max=2 \
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// RUN: | FileCheck %s --check-prefix=CHECK-256
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu %s -emit-llvm -o - \
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// RUN: -target-feature +sve -target-feature +bf16 -mvscale-min=4 -mvscale-max=4 \
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// RUN: | FileCheck %s --check-prefix=CHECK-512
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu %s -emit-llvm -o - \
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// RUN: -target-feature +sve -target-feature +bf16 -mvscale-min=8 -mvscale-max=8 \
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// RUN: | FileCheck %s --check-prefix=CHECK-1024
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu %s -emit-llvm -o - \
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// RUN: -target-feature +sve -target-feature +bf16 -mvscale-min=16 -mvscale-max=16 \
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// RUN: | FileCheck %s --check-prefix=CHECK-2048
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#define N __ARM_FEATURE_SVE_BITS
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typedef __SVInt8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N)));
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typedef __SVInt16_t fixed_int16_t __attribute__((arm_sve_vector_bits(N)));
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typedef __SVInt32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));
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typedef __SVInt64_t fixed_int64_t __attribute__((arm_sve_vector_bits(N)));
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typedef __SVUint8_t fixed_uint8_t __attribute__((arm_sve_vector_bits(N)));
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typedef __SVUint16_t fixed_uint16_t __attribute__((arm_sve_vector_bits(N)));
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typedef __SVUint32_t fixed_uint32_t __attribute__((arm_sve_vector_bits(N)));
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typedef __SVUint64_t fixed_uint64_t __attribute__((arm_sve_vector_bits(N)));
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typedef __SVFloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N)));
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typedef __SVFloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N)));
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typedef __SVFloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
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typedef __SVBFloat16_t fixed_bfloat16_t __attribute__((arm_sve_vector_bits(N)));
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typedef __SVBool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
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template <typename T> struct S {};
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// CHECK-128: _Z2f11SI9__SVE_VLSIu10__SVInt8_tLj128EEE
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// CHECK-256: _Z2f11SI9__SVE_VLSIu10__SVInt8_tLj256EEE
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// CHECK-512: _Z2f11SI9__SVE_VLSIu10__SVInt8_tLj512EEE
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// CHECK-1024: _Z2f11SI9__SVE_VLSIu10__SVInt8_tLj1024EEE
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// CHECK-2048: _Z2f11SI9__SVE_VLSIu10__SVInt8_tLj2048EEE
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void f1(S<fixed_int8_t>) {}
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// CHECK-128: _Z2f21SI9__SVE_VLSIu11__SVInt16_tLj128EEE
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// CHECK-256: _Z2f21SI9__SVE_VLSIu11__SVInt16_tLj256EEE
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// CHECK-512: _Z2f21SI9__SVE_VLSIu11__SVInt16_tLj512EEE
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// CHECK-1024: _Z2f21SI9__SVE_VLSIu11__SVInt16_tLj1024EEE
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// CHECK-2048: _Z2f21SI9__SVE_VLSIu11__SVInt16_tLj2048EEE
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void f2(S<fixed_int16_t>) {}
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// CHECK-128: _Z2f31SI9__SVE_VLSIu11__SVInt32_tLj128EEE
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// CHECK-256: _Z2f31SI9__SVE_VLSIu11__SVInt32_tLj256EEE
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// CHECK-512: _Z2f31SI9__SVE_VLSIu11__SVInt32_tLj512EEE
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// CHECK-1024: _Z2f31SI9__SVE_VLSIu11__SVInt32_tLj1024EEE
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// CHECK-2048: _Z2f31SI9__SVE_VLSIu11__SVInt32_tLj2048EEE
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void f3(S<fixed_int32_t>) {}
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// CHECK-128: _Z2f41SI9__SVE_VLSIu11__SVInt64_tLj128EEE
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// CHECK-256: _Z2f41SI9__SVE_VLSIu11__SVInt64_tLj256EEE
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// CHECK-512: _Z2f41SI9__SVE_VLSIu11__SVInt64_tLj512EEE
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// CHECK-1024: _Z2f41SI9__SVE_VLSIu11__SVInt64_tLj1024EEE
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// CHECK-2048: _Z2f41SI9__SVE_VLSIu11__SVInt64_tLj2048EEE
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void f4(S<fixed_int64_t>) {}
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// CHECK-128: _Z2f51SI9__SVE_VLSIu11__SVUint8_tLj128EEE
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// CHECK-256: _Z2f51SI9__SVE_VLSIu11__SVUint8_tLj256EEE
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// CHECK-512: _Z2f51SI9__SVE_VLSIu11__SVUint8_tLj512EEE
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// CHECK-1024: _Z2f51SI9__SVE_VLSIu11__SVUint8_tLj1024EEE
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// CHECK-2048: _Z2f51SI9__SVE_VLSIu11__SVUint8_tLj2048EEE
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void f5(S<fixed_uint8_t>) {}
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// CHECK-128: _Z2f61SI9__SVE_VLSIu12__SVUint16_tLj128EEE
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// CHECK-256: _Z2f61SI9__SVE_VLSIu12__SVUint16_tLj256EEE
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// CHECK-512: _Z2f61SI9__SVE_VLSIu12__SVUint16_tLj512EEE
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// CHECK-1024: _Z2f61SI9__SVE_VLSIu12__SVUint16_tLj1024EEE
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// CHECK-2048: _Z2f61SI9__SVE_VLSIu12__SVUint16_tLj2048EEE
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void f6(S<fixed_uint16_t>) {}
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// CHECK-128: _Z2f71SI9__SVE_VLSIu12__SVUint32_tLj128EEE
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// CHECK-256: _Z2f71SI9__SVE_VLSIu12__SVUint32_tLj256EEE
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// CHECK-512: _Z2f71SI9__SVE_VLSIu12__SVUint32_tLj512EEE
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// CHECK-1024: _Z2f71SI9__SVE_VLSIu12__SVUint32_tLj1024EEE
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// CHECK-2048: _Z2f71SI9__SVE_VLSIu12__SVUint32_tLj2048EEE
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void f7(S<fixed_uint32_t>) {}
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// CHECK-128: _Z2f81SI9__SVE_VLSIu12__SVUint64_tLj128EEE
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// CHECK-256: _Z2f81SI9__SVE_VLSIu12__SVUint64_tLj256EEE
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// CHECK-512: _Z2f81SI9__SVE_VLSIu12__SVUint64_tLj512EEE
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// CHECK-1024: _Z2f81SI9__SVE_VLSIu12__SVUint64_tLj1024EEE
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// CHECK-2048: _Z2f81SI9__SVE_VLSIu12__SVUint64_tLj2048EEE
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void f8(S<fixed_uint64_t>) {}
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// CHECK-128: _Z2f91SI9__SVE_VLSIu13__SVFloat16_tLj128EEE
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// CHECK-256: _Z2f91SI9__SVE_VLSIu13__SVFloat16_tLj256EEE
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// CHECK-512: _Z2f91SI9__SVE_VLSIu13__SVFloat16_tLj512EEE
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// CHECK-1024: _Z2f91SI9__SVE_VLSIu13__SVFloat16_tLj1024EEE
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// CHECK-2048: _Z2f91SI9__SVE_VLSIu13__SVFloat16_tLj2048EEE
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void f9(S<fixed_float16_t>) {}
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// CHECK-128: _Z3f101SI9__SVE_VLSIu13__SVFloat32_tLj128EEE
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// CHECK-256: _Z3f101SI9__SVE_VLSIu13__SVFloat32_tLj256EEE
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// CHECK-512: _Z3f101SI9__SVE_VLSIu13__SVFloat32_tLj512EEE
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// CHECK-1024: _Z3f101SI9__SVE_VLSIu13__SVFloat32_tLj1024EEE
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// CHECK-2048: _Z3f101SI9__SVE_VLSIu13__SVFloat32_tLj2048EEE
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void f10(S<fixed_float32_t>) {}
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// CHECK-128: _Z3f111SI9__SVE_VLSIu13__SVFloat64_tLj128EEE
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// CHECK-256: _Z3f111SI9__SVE_VLSIu13__SVFloat64_tLj256EEE
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// CHECK-512: _Z3f111SI9__SVE_VLSIu13__SVFloat64_tLj512EEE
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// CHECK-1024: _Z3f111SI9__SVE_VLSIu13__SVFloat64_tLj1024EEE
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// CHECK-2048: _Z3f111SI9__SVE_VLSIu13__SVFloat64_tLj2048EEE
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void f11(S<fixed_float64_t>) {}
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// CHECK-128: _Z3f121SI9__SVE_VLSIu14__SVBfloat16_tLj128EEE
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// CHECK-256: _Z3f121SI9__SVE_VLSIu14__SVBfloat16_tLj256EEE
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// CHECK-512: _Z3f121SI9__SVE_VLSIu14__SVBfloat16_tLj512EEE
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// CHECK-1024: _Z3f121SI9__SVE_VLSIu14__SVBfloat16_tLj1024EEE
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// CHECK-2048: _Z3f121SI9__SVE_VLSIu14__SVBfloat16_tLj2048EEE
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void f12(S<fixed_bfloat16_t>) {}
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// CHECK-128: _Z3f131SI9__SVE_VLSIu10__SVBool_tLj128EEE
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// CHECK-256: _Z3f131SI9__SVE_VLSIu10__SVBool_tLj256EEE
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// CHECK-512: _Z3f131SI9__SVE_VLSIu10__SVBool_tLj512EEE
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// CHECK-1024: _Z3f131SI9__SVE_VLSIu10__SVBool_tLj1024EEE
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// CHECK-2048: _Z3f131SI9__SVE_VLSIu10__SVBool_tLj2048EEE
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void f13(S<fixed_bool_t>) {}
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