8c1449a84d
This patch changes the kernels generated by OpenMP to have protected visibility. This is unlikely to change anything functionally. However, protected visibility better matches the behaviour of these GPU kernels. We do not expect any pending shared library load to preempt these kernels so we can specify a more restrictive visibility. Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D136198
226 lines
10 KiB
C++
226 lines
10 KiB
C++
// Only test codegen on target side, as private clause does not require any action on the host side
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// Test target codegen - host bc file has to be created first.
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY0 %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY0 %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
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// SIMD-ONLY0-NOT: {{__kmpc|__tgt}}
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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template<typename tx, typename ty>
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struct TT{
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tx X;
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ty Y;
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TT<tx, ty> operator*(const TT<tx, ty> &) { return *this; }
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};
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// TCHECK: [[S1:%.+]] = type { double }
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int foo(int n) {
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int a = 0;
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short aa = 0;
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float b[10];
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float bn[n];
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double c[5][10];
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double cn[5][n];
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TT<long long, char> d;
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#pragma omp target reduction(*:a)
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{
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}
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// TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(i32*{{.+}} %{{.+}})
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// TCHECK: [[A:%.+]] = alloca i{{[0-9]+}}*,
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// TCHECK: store {{.+}}, {{.+}} [[A]],
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// TCHECK: load i32*, i32** [[A]],
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// TCHECK: ret void
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#pragma omp target reduction(+:a)
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{
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a = 1;
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}
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// TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(i32*{{.+}} %{{.+}})
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// TCHECK: [[A:%.+]] = alloca i{{[0-9]+}}*,
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// TCHECK: store {{.+}}, {{.+}} [[A]],
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// TCHECK: [[REF:%.+]] = load i32*, i32** [[A]],
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// TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[REF]],
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// TCHECK: ret void
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#pragma omp target reduction(-:a, aa)
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{
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a = 1;
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aa = 1;
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}
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// TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(i32*{{.+}} [[A:%.+]], i16*{{.+}} [[AA:%.+]])
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// TCHECK: [[A:%.+]] = alloca i{{[0-9]+}}*,
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// TCHECK: [[AA:%.+]] = alloca i{{[0-9]+}}*,
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// TCHECK: store {{.+}}, {{.+}} [[A]],
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// TCHECK: store {{.+}}, {{.+}} [[AA]],
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// TCHECK: [[A_REF:%.+]] = load i32*, i32** [[A]],
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// TCHECK: [[AA_REF:%.+]] = load i16*, i16** [[AA]],
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// TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[A_REF]],
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// TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[AA_REF]],
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// TCHECK: ret void
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return a;
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}
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template<typename tx>
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tx ftemplate(int n) {
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tx a = 0;
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short aa = 0;
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tx b[10];
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#pragma omp target reduction(+:a,aa,b)
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{
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a = 1;
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aa = 1;
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b[2] = 1;
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}
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return a;
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}
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static
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int fstatic(int n) {
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int a = 0;
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short aa = 0;
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char aaa = 0;
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int b[10];
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#pragma omp target reduction(-:a,aa,aaa,b)
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{
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a = 1;
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aa = 1;
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aaa = 1;
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b[2] = 1;
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}
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return a;
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}
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// TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(i32*{{.+}}, i16*{{.+}}, i8*{{.+}}, [10 x i32]*{{.+}})
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// TCHECK: [[A:%.+]] = alloca i{{[0-9]+}}*,
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// TCHECK: [[A2:%.+]] = alloca i{{[0-9]+}}*,
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// TCHECK: [[A3:%.+]] = alloca i{{[0-9]+}}*,
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// TCHECK: [[B:%.+]] = alloca [10 x i{{[0-9]+}}]*,
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// TCHECK: store {{.+}}, {{.+}} [[A]],
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// TCHECK: store {{.+}}, {{.+}} [[A2]],
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// TCHECK: store {{.+}}, {{.+}} [[A3]],
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// TCHECK: store {{.+}}, {{.+}} [[B]],
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// TCHECK: [[A_REF:%.+]] = load i32*, i32** [[A]],
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// TCHECK: [[AA_REF:%.+]] = load i16*, i16** [[AA]],
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// TCHECK: [[A3_REF:%.+]] = load i8*, i8** [[A3]],
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// TCHECK: [[B_REF:%.+]] = load {{.+}}*, {{.+}}** [[B]],
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// TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[A_REF]],
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// TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[AA_REF]],
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// TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[A3_REF]],
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// TCHECK: [[B_GEP:%.+]] = getelementptr inbounds [10 x i{{[0-9]+}}], [10 x i{{[0-9]+}}]* [[B_REF]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
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// TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[B_GEP]],
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// TCHECK: ret void
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struct S1 {
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double a;
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int r1(int n){
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int b = n+1;
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short int c[2][n];
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#pragma omp target reduction(max:b,c)
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{
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this->a = (double)b + 1.5;
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c[1][1] = ++a;
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}
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return c[1][1] + (int)b;
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}
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// TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}([[S1]]* noundef [[TH:%.+]], i32*{{.+}}, i{{[0-9]+}} noundef [[VLA:%.+]], i{{[0-9]+}} noundef [[VLA1:%.+]], i16*{{.+}})
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// TCHECK: [[TH_ADDR:%.+]] = alloca [[S1]]*,
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// TCHECK: [[B_ADDR:%.+]] = alloca i{{[0-9]+}}*,
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// TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}},
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// TCHECK: [[VLA_ADDR2:%.+]] = alloca i{{[0-9]+}},
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// TCHECK: [[C_ADDR:%.+]] = alloca i{{[0-9]+}}*,
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// TCHECK: store [[S1]]* [[TH]], [[S1]]** [[TH_ADDR]],
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// TCHECK: store i{{[0-9]+}}* {{.+}}, i{{[0-9]+}}** [[B_ADDR]],
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// TCHECK: store i{{[0-9]+}} [[VLA]], i{{[0-9]+}}* [[VLA_ADDR]],
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// TCHECK: store i{{[0-9]+}} [[VLA1]], i{{[0-9]+}}* [[VLA_ADDR2]],
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// TCHECK: store i{{[0-9]+}}* {{.+}}, i{{[0-9]+}}** [[C_ADDR]],
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// TCHECK: [[TH_ADDR_REF:%.+]] = load [[S1]]*, [[S1]]** [[TH_ADDR]],
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// TCHECK: [[B_REF:%.+]] = load i{{[0-9]+}}*, i{{[0-9]+}}** [[B_ADDR]],
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// TCHECK: [[VLA_ADDR_REF:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[VLA_ADDR]],
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// TCHECK: [[VLA_ADDR_REF2:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[VLA_ADDR2]],
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// TCHECK: [[C_REF:%.+]] = load i{{[0-9]+}}*, i{{[0-9]+}}** [[C_ADDR]],
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// this->a = (double)b + 1.5;
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// TCHECK: [[B_VAL:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[B_REF]],
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// TCHECK: [[B_CONV:%.+]] = sitofp i{{[0-9]+}} [[B_VAL]] to double
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// TCHECK: [[NEW_A_VAL:%.+]] = fadd double [[B_CONV]], 1.5{{.+}}+00
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// TCHECK: [[A_FIELD:%.+]] = getelementptr inbounds [[S1]], [[S1]]* [[TH_ADDR_REF]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
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// TCHECK: store double [[NEW_A_VAL]], double* [[A_FIELD]],
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// c[1][1] = ++a;
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// TCHECK: [[A_FIELD4:%.+]] = getelementptr inbounds [[S1]], [[S1]]* [[TH_ADDR_REF]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
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// TCHECK: [[A_FIELD4_VAL:%.+]] = load double, double* [[A_FIELD4]],
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// TCHECK: [[A_FIELD_INC:%.+]] = fadd double [[A_FIELD4_VAL]], 1.0{{.+}}+00
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// TCHECK: store double [[A_FIELD_INC]], double* [[A_FIELD4]],
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// TCHECK: [[A_FIELD_INC_CONV:%.+]] = fptosi double [[A_FIELD_INC]] to i{{[0-9]+}}
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// TCHECK: [[C_IND:%.+]] = mul{{.+}} i{{[0-9]+}} 1, [[VLA_ADDR_REF2]]
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// TCHECK: [[C_1_REF:%.+]] = getelementptr inbounds i{{[0-9]+}}, i{{[0-9]+}}* [[C_REF]], i{{[0-9]+}} [[C_IND]]
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// TCHECK: [[C_1_1_REF:%.+]] = getelementptr inbounds i{{[0-9]+}}, i{{[0-9]+}}* [[C_1_REF]], i{{[0-9]+}} 1
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// TCHECK: store i{{[0-9]+}} [[A_FIELD_INC_CONV]], i{{[0-9]+}}* [[C_1_1_REF]],
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// finish
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// TCHECK: ret void
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};
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int bar(int n){
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int a = 0;
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a += foo(n);
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S1 S;
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a += S.r1(n);
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a += fstatic(n);
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a += ftemplate<int>(n);
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return a;
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}
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// template
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// TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(i{{[0-9]+}}*{{.+}}, i{{[0-9]+}}*{{.+}}, [10 x i32]*{{.+}})
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// TCHECK: [[A:%.+]] = alloca i{{[0-9]+}}*,
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// TCHECK: [[A2:%.+]] = alloca i{{[0-9]+}}*,
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// TCHECK: [[B:%.+]] = alloca [10 x i{{[0-9]+}}]*,
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// TCHECK: store {{.+}}, {{.+}} [[A]],
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// TCHECK: store {{.+}}, {{.+}} [[A2]],
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// TCHECK: store {{.+}}, {{.+}} [[B]],
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// TCHECK: [[A_REF:%.+]] = load i32*, i32** [[A]],
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// TCHECK: [[AA_REF:%.+]] = load i16*, i16** [[AA]],
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// TCHECK: [[B_REF:%.+]] = load {{.+}}*, {{.+}}** [[B]],
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// TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[A_REF]],
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// TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[AA_REF]],
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// TCHECK: [[B_GEP:%.+]] = getelementptr inbounds [10 x i{{[0-9]+}}], [10 x i{{[0-9]+}}]* [[B_REF]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
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// TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[B_GEP]],
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// TCHECK: ret void
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#endif
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