ad7bcda940
To build complex binding upon instruction trace, additional metadata 'instruction type' is needed. This diff has followings: - Add a flag -k / --kind for instruction dump - Remove SetGranularity and SetIgnoreErros from Trace cursor Sample output: ``` (lldb) thread trace dump instruction -k thread #1: tid = 3198805 libc.so.6`_IO_puts + 356 2107: 0x00007ffff7163594 ( return) retq 2106: 0x00007ffff7163592 ( other) popq %r13 2105: 0x00007ffff7163590 ( other) popq %r12 2104: 0x00007ffff716358f ( other) popq %rbp 2103: 0x00007ffff716358e ( other) popq %rbx 2102: 0x00007ffff716358c ( other) movl %ebx, %eax 2101: 0x00007ffff7163588 ( other) addq $0x8, %rsp 2100: 0x00007ffff7163570 ( cond jump) je 0x89588 ; <+344> 2099: 0x00007ffff716356e ( other) decl (%rdx) 2098: 0x00007ffff7163565 ( cond jump) je 0x8956e ; <+318> 2097: 0x00007ffff716355e ( other) cmpl $0x0, 0x33c02b(%rip) ; __libc_multiple_threads 2096: 0x00007ffff7163556 ( other) movq $0x0, 0x8(%rdx) 2095: 0x00007ffff7163554 ( cond jump) jne 0x89588 ; <+344> 2094: 0x00007ffff7163550 ( other) subl $0x1, 0x4(%rdx) 2093: 0x00007ffff7163549 ( other) movq 0x88(%rbp), %rdx 2092: 0x00007ffff7163547 ( cond jump) jne 0x89588 ; <+344> 2091: 0x00007ffff7163540 ( other) testl $0x8000, (%rbp) ; imm = 0x8000 2090: 0x00007ffff716353c ( other) cmovaq %rax, %rbx 2089: 0x00007ffff7163535 ( other) cmpq $0x7fffffff, %rbx ; imm = 0x7FFFFFFF 2088: 0x00007ffff7163530 ( other) movl $0x7fffffff, %eax ; imm = 0x7FFFFFFF ``` Reviewed By: wallace Differential Revision: https://reviews.llvm.org/D128477
80 lines
2.5 KiB
C++
80 lines
2.5 KiB
C++
//===-- TestArm64Disassembly.cpp ------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "gtest/gtest.h"
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#include "lldb/Core/Address.h"
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#include "lldb/Core/Disassembler.h"
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#include "lldb/Utility/ArchSpec.h"
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#include "lldb/Target/ExecutionContext.h"
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#include "Plugins/Disassembler/LLVMC/DisassemblerLLVMC.h"
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#include "llvm/Support/TargetSelect.h"
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using namespace lldb;
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using namespace lldb_private;
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class TestArm64Disassembly : public testing::Test {
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public:
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static void SetUpTestCase();
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static void TearDownTestCase();
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// virtual void SetUp() override { }
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// virtual void TearDown() override { }
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protected:
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};
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void TestArm64Disassembly::SetUpTestCase() {
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llvm::InitializeAllTargets();
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llvm::InitializeAllAsmPrinters();
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llvm::InitializeAllTargetMCs();
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llvm::InitializeAllDisassemblers();
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DisassemblerLLVMC::Initialize();
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}
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void TestArm64Disassembly::TearDownTestCase() {
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DisassemblerLLVMC::Terminate();
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}
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TEST_F(TestArm64Disassembly, TestArmv81Instruction) {
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ArchSpec arch("arm64-apple-ios");
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const unsigned num_of_instructions = 2;
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uint8_t data[] = {
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0xff, 0x43, 0x00, 0xd1, // 0xd10043ff : sub sp, sp, #0x10
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0x62, 0x7c, 0xa1, 0xc8, // 0xc8a17c62 : cas x1, x2, [x3] (cas defined in ARM v8.1 & newer)
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};
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DisassemblerSP disass_sp;
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Address start_addr(0x100);
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disass_sp = Disassembler::DisassembleBytes(arch, nullptr, nullptr, start_addr,
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&data, sizeof (data), num_of_instructions, false);
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// If we failed to get a disassembler, we can assume it is because
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// the llvm we linked against was not built with the ARM target,
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// and we should skip these tests without marking anything as failing.
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if (disass_sp) {
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const InstructionList inst_list (disass_sp->GetInstructionList());
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EXPECT_EQ (num_of_instructions, inst_list.GetSize());
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InstructionSP inst_sp;
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const char *mnemonic;
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ExecutionContext exe_ctx (nullptr, nullptr, nullptr);
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inst_sp = inst_list.GetInstructionAtIndex (0);
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mnemonic = inst_sp->GetMnemonic(&exe_ctx);
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ASSERT_STREQ ("sub", mnemonic);
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inst_sp = inst_list.GetInstructionAtIndex (1);
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mnemonic = inst_sp->GetMnemonic(&exe_ctx);
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ASSERT_STREQ ("cas", mnemonic);
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}
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}
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