e10e936315
This patch makes two notable changes to the MIR debug info representation,
which result in different MIR output but identical final DWARF output (NFC
w.r.t. the full compilation). The two changes are:
* The introduction of a new MachineOperand type, MO_DbgInstrRef, which
consists of two unsigned numbers that are used to index an instruction
and an output operand within that instruction, having a meaning
identical to first two operands of the current DBG_INSTR_REF
instruction. This operand is only used in DBG_INSTR_REF (see below).
* A change in syntax for the DBG_INSTR_REF instruction, shuffling the
operands to make it resemble DBG_VALUE_LIST instead of DBG_VALUE,
and replacing the first two operands with a single MO_DbgInstrRef-type
operand.
This patch is the first of a set that will allow DBG_INSTR_REF
instructions to refer to multiple machine locations in the same manner
as DBG_VALUE_LIST.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D129372
238 lines
9.8 KiB
C++
238 lines
9.8 KiB
C++
//===- lib/CodeGen/MachineStableHash.cpp ----------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Stable hashing for MachineInstr and MachineOperand. Useful or getting a
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// hash across runs, modules, etc.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineStableHash.h"
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DenseMapInfo.h"
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#include "llvm/ADT/Hashing.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/ilist_iterator.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBundleIterator.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Register.h"
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#include "llvm/CodeGen/StableHashing.h"
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#include "llvm/Config/llvm-config.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/Alignment.h"
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#include "llvm/Support/ErrorHandling.h"
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#define DEBUG_TYPE "machine-stable-hash"
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using namespace llvm;
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STATISTIC(StableHashBailingMachineBasicBlock,
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"Number of encountered unsupported MachineOperands that were "
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"MachineBasicBlocks while computing stable hashes");
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STATISTIC(StableHashBailingConstantPoolIndex,
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"Number of encountered unsupported MachineOperands that were "
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"ConstantPoolIndex while computing stable hashes");
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STATISTIC(StableHashBailingTargetIndexNoName,
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"Number of encountered unsupported MachineOperands that were "
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"TargetIndex with no name");
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STATISTIC(StableHashBailingGlobalAddress,
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"Number of encountered unsupported MachineOperands that were "
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"GlobalAddress while computing stable hashes");
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STATISTIC(StableHashBailingBlockAddress,
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"Number of encountered unsupported MachineOperands that were "
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"BlockAddress while computing stable hashes");
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STATISTIC(StableHashBailingMetadataUnsupported,
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"Number of encountered unsupported MachineOperands that were "
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"Metadata of an unsupported kind while computing stable hashes");
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stable_hash llvm::stableHashValue(const MachineOperand &MO) {
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switch (MO.getType()) {
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case MachineOperand::MO_Register:
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if (Register::isVirtualRegister(MO.getReg())) {
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const MachineRegisterInfo &MRI = MO.getParent()->getMF()->getRegInfo();
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SmallVector<unsigned> DefOpcodes;
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for (auto &Def : MRI.def_instructions(MO.getReg()))
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DefOpcodes.push_back(Def.getOpcode());
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return hash_combine_range(DefOpcodes.begin(), DefOpcodes.end());
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}
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// Register operands don't have target flags.
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return stable_hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(),
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MO.isDef());
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case MachineOperand::MO_Immediate:
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return stable_hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
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case MachineOperand::MO_CImmediate:
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case MachineOperand::MO_FPImmediate: {
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auto Val = MO.isCImm() ? MO.getCImm()->getValue()
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: MO.getFPImm()->getValueAPF().bitcastToAPInt();
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auto ValHash =
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stable_hash_combine_array(Val.getRawData(), Val.getNumWords());
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return hash_combine(MO.getType(), MO.getTargetFlags(), ValHash);
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}
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case MachineOperand::MO_MachineBasicBlock:
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StableHashBailingMachineBasicBlock++;
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return 0;
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case MachineOperand::MO_ConstantPoolIndex:
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StableHashBailingConstantPoolIndex++;
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return 0;
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case MachineOperand::MO_BlockAddress:
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StableHashBailingBlockAddress++;
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return 0;
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case MachineOperand::MO_Metadata:
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StableHashBailingMetadataUnsupported++;
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return 0;
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case MachineOperand::MO_GlobalAddress:
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StableHashBailingGlobalAddress++;
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return 0;
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case MachineOperand::MO_TargetIndex: {
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if (const char *Name = MO.getTargetIndexName())
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return stable_hash_combine(MO.getType(), MO.getTargetFlags(),
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stable_hash_combine_string(Name),
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MO.getOffset());
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StableHashBailingTargetIndexNoName++;
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return 0;
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}
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case MachineOperand::MO_FrameIndex:
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case MachineOperand::MO_JumpTableIndex:
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return stable_hash_combine(MO.getType(), MO.getTargetFlags(),
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MO.getIndex());
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case MachineOperand::MO_ExternalSymbol:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
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stable_hash_combine_string(MO.getSymbolName()));
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case MachineOperand::MO_RegisterMask:
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case MachineOperand::MO_RegisterLiveOut: {
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if (const MachineInstr *MI = MO.getParent()) {
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if (const MachineBasicBlock *MBB = MI->getParent()) {
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if (const MachineFunction *MF = MBB->getParent()) {
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const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
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unsigned RegMaskSize =
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MachineOperand::getRegMaskSize(TRI->getNumRegs());
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const uint32_t *RegMask = MO.getRegMask();
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std::vector<llvm::stable_hash> RegMaskHashes(RegMask,
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RegMask + RegMaskSize);
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return hash_combine(MO.getType(), MO.getTargetFlags(),
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stable_hash_combine_array(RegMaskHashes.data(),
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RegMaskHashes.size()));
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}
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}
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}
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assert(0 && "MachineOperand not associated with any MachineFunction");
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return hash_combine(MO.getType(), MO.getTargetFlags());
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}
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case MachineOperand::MO_ShuffleMask: {
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std::vector<llvm::stable_hash> ShuffleMaskHashes;
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llvm::transform(
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MO.getShuffleMask(), std::back_inserter(ShuffleMaskHashes),
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[](int S) -> llvm::stable_hash { return llvm::stable_hash(S); });
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return hash_combine(MO.getType(), MO.getTargetFlags(),
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stable_hash_combine_array(ShuffleMaskHashes.data(),
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ShuffleMaskHashes.size()));
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}
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case MachineOperand::MO_MCSymbol: {
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auto SymbolName = MO.getMCSymbol()->getName();
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return hash_combine(MO.getType(), MO.getTargetFlags(),
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stable_hash_combine_string(SymbolName));
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}
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case MachineOperand::MO_CFIIndex:
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return stable_hash_combine(MO.getType(), MO.getTargetFlags(),
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MO.getCFIIndex());
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case MachineOperand::MO_IntrinsicID:
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return stable_hash_combine(MO.getType(), MO.getTargetFlags(),
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MO.getIntrinsicID());
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case MachineOperand::MO_Predicate:
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return stable_hash_combine(MO.getType(), MO.getTargetFlags(),
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MO.getPredicate());
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case MachineOperand::MO_DbgInstrRef:
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return stable_hash_combine(MO.getType(), MO.getInstrRefInstrIndex(),
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MO.getInstrRefOpIndex());
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}
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llvm_unreachable("Invalid machine operand type");
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}
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/// A stable hash value for machine instructions.
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/// Returns 0 if no stable hash could be computed.
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/// The hashing and equality testing functions ignore definitions so this is
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/// useful for CSE, etc.
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stable_hash llvm::stableHashValue(const MachineInstr &MI, bool HashVRegs,
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bool HashConstantPoolIndices,
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bool HashMemOperands) {
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// Build up a buffer of hash code components.
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SmallVector<stable_hash, 16> HashComponents;
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HashComponents.reserve(MI.getNumOperands() + MI.getNumMemOperands() + 2);
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HashComponents.push_back(MI.getOpcode());
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HashComponents.push_back(MI.getFlags());
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for (const MachineOperand &MO : MI.operands()) {
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if (!HashVRegs && MO.isReg() && MO.isDef() &&
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Register::isVirtualRegister(MO.getReg()))
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continue; // Skip virtual register defs.
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if (MO.isCPI()) {
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HashComponents.push_back(stable_hash_combine(
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MO.getType(), MO.getTargetFlags(), MO.getIndex()));
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continue;
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}
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stable_hash StableHash = stableHashValue(MO);
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if (!StableHash)
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return 0;
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HashComponents.push_back(StableHash);
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}
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for (const auto *Op : MI.memoperands()) {
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if (!HashMemOperands)
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break;
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HashComponents.push_back(static_cast<unsigned>(Op->getSize()));
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HashComponents.push_back(static_cast<unsigned>(Op->getFlags()));
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HashComponents.push_back(static_cast<unsigned>(Op->getOffset()));
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HashComponents.push_back(static_cast<unsigned>(Op->getSuccessOrdering()));
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HashComponents.push_back(static_cast<unsigned>(Op->getAddrSpace()));
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HashComponents.push_back(static_cast<unsigned>(Op->getSyncScopeID()));
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HashComponents.push_back(static_cast<unsigned>(Op->getBaseAlign().value()));
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HashComponents.push_back(static_cast<unsigned>(Op->getFailureOrdering()));
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}
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return stable_hash_combine_range(HashComponents.begin(),
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HashComponents.end());
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}
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stable_hash llvm::stableHashValue(const MachineBasicBlock &MBB) {
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SmallVector<stable_hash> HashComponents;
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// TODO: Hash more stuff like block alignment and branch probabilities.
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for (const auto &MI : MBB)
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HashComponents.push_back(stableHashValue(MI));
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return stable_hash_combine_range(HashComponents.begin(),
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HashComponents.end());
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}
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stable_hash llvm::stableHashValue(const MachineFunction &MF) {
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SmallVector<stable_hash> HashComponents;
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// TODO: Hash lots more stuff like function alignment and stack objects.
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for (const auto &MBB : MF)
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HashComponents.push_back(stableHashValue(MBB));
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return stable_hash_combine_range(HashComponents.begin(),
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HashComponents.end());
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}
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