Ties Stuij 0b066e02a6 [AArch64] add GlobalIsel support for scalar CNT instruction ...

When feature CSSC is available we should use instruction CNT for s32, s64 and
s128 types in GlobalIsel's G_CTPOP.

spec:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/CNT--Count-bits-

Reviewed By: aemerson

Differential Revision: https://reviews.llvm.org/D139417

2023-01-06 11:08:34 +00:00

..

AArch64CallLowering.cpp

Move from llvm::makeArrayRef to ArrayRef deduction guides - llvm/ part

2023-01-05 14:11:08 +01:00

AArch64CallLowering.h

Revert "[AArch64][GlobalISel] Lower formal arguments of AAPCS & ms_abi variadic functions."

2022-12-13 11:37:35 +02:00

AArch64GlobalISelUtils.cpp

[CodeGen] llvm::Optional => std::optional

2022-12-13 09:06:36 +00:00

AArch64GlobalISelUtils.h

[CodeGen] llvm::Optional => std::optional

2022-12-13 09:06:36 +00:00

AArch64InstructionSelector.cpp

Revert "[AArch64][GlobalISel] Lower formal arguments of AAPCS & ms_abi variadic functions."

2022-12-13 11:37:35 +02:00

AArch64LegalizerInfo.cpp

[AArch64] add GlobalIsel support for scalar CNT instruction

2023-01-06 11:08:34 +00:00

AArch64LegalizerInfo.h

Revert "Revert "[AArch64][GlobalISel][Legalizer] Legalize G_SHUFFLE_VECTOR with different lengths""

2022-12-15 11:19:24 -08:00

AArch64O0PreLegalizerCombiner.cpp

[GlobalISel] Allow prelegalizer combiners to have access to LegalizerInfo.

2022-10-03 07:36:18 +01:00

AArch64PostLegalizerCombiner.cpp

Revert "[AArch64][GlobalISel] Fold away lowered vector sign-extend of vector compares."

2022-10-04 11:03:02 +01:00

AArch64PostLegalizerLowering.cpp

AArch64: emit fcmp ord %a, zeroinitializer as a single fcmeq.

2022-12-07 19:17:30 +00:00

AArch64PostSelectOptimize.cpp

[AArch64][GlobalISel] Add a simple cross-regclass copy optimization post-selection.

2022-11-01 16:09:21 -07:00

AArch64PreLegalizerCombiner.cpp

[GlobalISel] Allow prelegalizer combiners to have access to LegalizerInfo.

2022-10-03 07:36:18 +01:00

AArch64RegisterBankInfo.cpp

[AArch64] SME2 Single-multi vector ternary int/FP 2 and 4 registers

2022-10-19 17:49:48 +01:00

AArch64RegisterBankInfo.h

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