63390dccd8
Small QoL change to allow Predicates to be used in GICombineRule. Currently only one combine in the AMDGPU backend makes use of it. The implementation is pretty simple to get started but of course we can expand this later on and optimize predicate checking better if needed. Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D136681
136 lines
6.1 KiB
TableGen
136 lines
6.1 KiB
TableGen
//=- AMDGPUCombine.td - Define AMDGPU Combine Rules ----------*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/GlobalISel/Combine.td"
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// TODO: This really belongs after legalization after scalarization.
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def fmin_fmax_legacy_matchdata : GIDefMatchData<"AMDGPUPostLegalizerCombinerHelper::FMinFMaxLegacyInfo">;
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let Predicates = [HasFminFmaxLegacy] in
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def fcmp_select_to_fmin_fmax_legacy : GICombineRule<
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(defs root:$select, fmin_fmax_legacy_matchdata:$matchinfo),
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(match (wip_match_opcode G_SELECT):$select,
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[{ return PostLegalizerHelper.matchFMinFMaxLegacy(*${select}, ${matchinfo}); }]),
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(apply [{ PostLegalizerHelper.applySelectFCmpToFMinToFMaxLegacy(*${select}, ${matchinfo}); }])>;
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def uchar_to_float : GICombineRule<
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(defs root:$itofp),
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(match (wip_match_opcode G_UITOFP, G_SITOFP):$itofp,
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[{ return PostLegalizerHelper.matchUCharToFloat(*${itofp}); }]),
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(apply [{ PostLegalizerHelper.applyUCharToFloat(*${itofp}); }])>;
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def rcp_sqrt_to_rsq : GICombineRule<
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(defs root:$rcp, build_fn_matchinfo:$matchinfo),
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(match (wip_match_opcode G_INTRINSIC, G_FSQRT):$rcp,
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[{ return PostLegalizerHelper.matchRcpSqrtToRsq(*${rcp}, ${matchinfo}); }]),
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(apply [{ Helper.applyBuildFn(*${rcp}, ${matchinfo}); }])>;
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def cvt_f32_ubyteN_matchdata : GIDefMatchData<"AMDGPUPostLegalizerCombinerHelper::CvtF32UByteMatchInfo">;
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def cvt_f32_ubyteN : GICombineRule<
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(defs root:$cvt_f32_ubyteN, cvt_f32_ubyteN_matchdata:$matchinfo),
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(match (wip_match_opcode G_AMDGPU_CVT_F32_UBYTE0,
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G_AMDGPU_CVT_F32_UBYTE1,
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G_AMDGPU_CVT_F32_UBYTE2,
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G_AMDGPU_CVT_F32_UBYTE3):$cvt_f32_ubyteN,
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[{ return PostLegalizerHelper.matchCvtF32UByteN(*${cvt_f32_ubyteN}, ${matchinfo}); }]),
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(apply [{ PostLegalizerHelper.applyCvtF32UByteN(*${cvt_f32_ubyteN}, ${matchinfo}); }])>;
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def clamp_i64_to_i16_matchdata : GIDefMatchData<"AMDGPUPreLegalizerCombinerHelper::ClampI64ToI16MatchInfo">;
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def clamp_i64_to_i16 : GICombineRule<
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(defs root:$clamp_i64_to_i16, clamp_i64_to_i16_matchdata:$matchinfo),
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(match (wip_match_opcode G_TRUNC):$clamp_i64_to_i16,
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[{ return PreLegalizerHelper.matchClampI64ToI16(*${clamp_i64_to_i16}, MRI, *MF, ${matchinfo}); }]),
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(apply [{ PreLegalizerHelper.applyClampI64ToI16(*${clamp_i64_to_i16}, ${matchinfo}); }])>;
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def med3_matchdata : GIDefMatchData<"AMDGPURegBankCombinerHelper::Med3MatchInfo">;
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def int_minmax_to_med3 : GICombineRule<
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(defs root:$min_or_max, med3_matchdata:$matchinfo),
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(match (wip_match_opcode G_SMAX,
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G_SMIN,
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G_UMAX,
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G_UMIN):$min_or_max,
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[{ return RegBankHelper.matchIntMinMaxToMed3(*${min_or_max}, ${matchinfo}); }]),
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(apply [{ RegBankHelper.applyMed3(*${min_or_max}, ${matchinfo}); }])>;
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def fp_minmax_to_med3 : GICombineRule<
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(defs root:$min_or_max, med3_matchdata:$matchinfo),
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(match (wip_match_opcode G_FMAXNUM,
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G_FMINNUM,
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G_FMAXNUM_IEEE,
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G_FMINNUM_IEEE):$min_or_max,
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[{ return RegBankHelper.matchFPMinMaxToMed3(*${min_or_max}, ${matchinfo}); }]),
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(apply [{ RegBankHelper.applyMed3(*${min_or_max}, ${matchinfo}); }])>;
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def fp_minmax_to_clamp : GICombineRule<
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(defs root:$min_or_max, register_matchinfo:$matchinfo),
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(match (wip_match_opcode G_FMAXNUM,
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G_FMINNUM,
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G_FMAXNUM_IEEE,
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G_FMINNUM_IEEE):$min_or_max,
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[{ return RegBankHelper.matchFPMinMaxToClamp(*${min_or_max}, ${matchinfo}); }]),
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(apply [{ RegBankHelper.applyClamp(*${min_or_max}, ${matchinfo}); }])>;
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def fmed3_intrinsic_to_clamp : GICombineRule<
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(defs root:$fmed3, register_matchinfo:$matchinfo),
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(match (wip_match_opcode G_INTRINSIC):$fmed3,
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[{ return RegBankHelper.matchFPMed3ToClamp(*${fmed3}, ${matchinfo}); }]),
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(apply [{ RegBankHelper.applyClamp(*${fmed3}, ${matchinfo}); }])>;
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def remove_fcanonicalize_matchinfo : GIDefMatchData<"Register">;
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def remove_fcanonicalize : GICombineRule<
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(defs root:$fcanonicalize, remove_fcanonicalize_matchinfo:$matchinfo),
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(match (wip_match_opcode G_FCANONICALIZE):$fcanonicalize,
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[{ return PostLegalizerHelper.matchRemoveFcanonicalize(*${fcanonicalize}, ${matchinfo}); }]),
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(apply [{ Helper.replaceSingleDefInstWithReg(*${fcanonicalize}, ${matchinfo}); }])>;
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def foldable_fneg_matchdata : GIDefMatchData<"MachineInstr *">;
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def foldable_fneg : GICombineRule<
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(defs root:$ffn, foldable_fneg_matchdata:$matchinfo),
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(match (wip_match_opcode G_FNEG):$ffn,
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[{ return Helper.matchFoldableFneg(*${ffn}, ${matchinfo}); }]),
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(apply [{ Helper.applyFoldableFneg(*${ffn}, ${matchinfo}); }])>;
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// Combines which should only apply on SI/VI
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def gfx6gfx7_combines : GICombineGroup<[fcmp_select_to_fmin_fmax_legacy]>;
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def AMDGPUPreLegalizerCombinerHelper: GICombinerHelper<
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"AMDGPUGenPreLegalizerCombinerHelper",
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[all_combines, clamp_i64_to_i16, foldable_fneg]> {
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let DisableRuleOption = "amdgpuprelegalizercombiner-disable-rule";
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let StateClass = "AMDGPUPreLegalizerCombinerHelperState";
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let AdditionalArguments = [];
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}
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def AMDGPUPostLegalizerCombinerHelper: GICombinerHelper<
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"AMDGPUGenPostLegalizerCombinerHelper",
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[all_combines, gfx6gfx7_combines,
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uchar_to_float, cvt_f32_ubyteN, remove_fcanonicalize, foldable_fneg,
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rcp_sqrt_to_rsq]> {
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let DisableRuleOption = "amdgpupostlegalizercombiner-disable-rule";
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let StateClass = "AMDGPUPostLegalizerCombinerHelperState";
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let AdditionalArguments = [];
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}
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def AMDGPURegBankCombinerHelper : GICombinerHelper<
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"AMDGPUGenRegBankCombinerHelper",
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[zext_trunc_fold, int_minmax_to_med3, ptr_add_immed_chain,
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fp_minmax_to_clamp, fp_minmax_to_med3, fmed3_intrinsic_to_clamp]> {
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let DisableRuleOption = "amdgpuregbankcombiner-disable-rule";
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let StateClass = "AMDGPURegBankCombinerHelperState";
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let AdditionalArguments = [];
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}
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