69e75ae695
This fixes what I consider to be an API flaw I've tripped over multiple times. The point this is constructed isn't well defined, so depending on where this is first called, you can conclude different information based on the MachineFunction. For example, the AMDGPU implementation inspected the MachineFrameInfo on construction for the stack objects and if the frame has calls. This kind of worked in SelectionDAG which visited all allocas up front, but broke in GlobalISel which hasn't visited any of the IR when arguments are lowered. I've run into similar problems before with the MIR parser and trying to make use of other MachineFunction fields, so I think it's best to just categorically disallow dependency on the MachineFunction state in the constructor and to always construct this at the same time as the MachineFunction itself. A missing feature I still could use is a way to access an custom analysis pass on the IR here.
112 lines
3.7 KiB
C++
112 lines
3.7 KiB
C++
//===- MipsTargetMachine.h - Define TargetMachine for Mips ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the Mips specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSTARGETMACHINE_H
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#define LLVM_LIB_TARGET_MIPS_MIPSTARGETMACHINE_H
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#include "MCTargetDesc/MipsABIInfo.h"
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#include "MipsSubtarget.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Target/TargetMachine.h"
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#include <memory>
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#include <optional>
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namespace llvm {
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class MipsTargetMachine : public LLVMTargetMachine {
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bool isLittle;
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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// Selected ABI
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MipsABIInfo ABI;
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const MipsSubtarget *Subtarget;
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MipsSubtarget DefaultSubtarget;
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MipsSubtarget NoMips16Subtarget;
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MipsSubtarget Mips16Subtarget;
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mutable StringMap<std::unique_ptr<MipsSubtarget>> SubtargetMap;
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public:
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MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
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bool JIT, bool isLittle);
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~MipsTargetMachine() override;
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TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
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const MipsSubtarget *getSubtargetImpl() const {
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if (Subtarget)
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return Subtarget;
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return &DefaultSubtarget;
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}
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const MipsSubtarget *getSubtargetImpl(const Function &F) const override;
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/// Reset the subtarget for the Mips target.
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void resetSubtarget(MachineFunction *MF);
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// Pass Pipeline Configuration
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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TargetLoweringObjectFile *getObjFileLowering() const override {
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return TLOF.get();
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}
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MachineFunctionInfo *
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createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
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const TargetSubtargetInfo *STI) const override;
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/// Returns true if a cast between SrcAS and DestAS is a noop.
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bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
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// Mips doesn't have any special address spaces so we just reserve
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// the first 256 for software use (e.g. OpenCL) and treat casts
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// between them as noops.
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return SrcAS < 256 && DestAS < 256;
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}
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bool isLittleEndian() const { return isLittle; }
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const MipsABIInfo &getABI() const { return ABI; }
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};
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/// Mips32/64 big endian target machine.
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///
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class MipsebTargetMachine : public MipsTargetMachine {
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virtual void anchor();
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public:
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MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
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bool JIT);
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};
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/// Mips32/64 little endian target machine.
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///
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class MipselTargetMachine : public MipsTargetMachine {
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virtual void anchor();
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public:
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MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
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bool JIT);
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_MIPS_MIPSTARGETMACHINE_H
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