9df924a634
A new register class as well as a number of related subregisters are being added to Future CPU. These registers are Dense Math Registers (DMR) and are 1024 bits long. These regsiters can also be used in consecutive pairs which leads to a register that is 2048 bits. This patch also adds 7 new instructions that use these registers. More instructions will be added in future patches. Reviewed By: amyk, saghir Differential Revision: https://reviews.llvm.org/D136366
219 lines
8.9 KiB
C++
219 lines
8.9 KiB
C++
//===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides PowerPC specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
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#define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
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// GCC #defines PPC on Linux but we use it as our namespace name
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#undef PPC
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/MathExtras.h"
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#include <cstdint>
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#include <memory>
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namespace llvm {
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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class MCObjectTargetWriter;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class MCTargetOptions;
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class Target;
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MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
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MCContext &Ctx);
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MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &Options);
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/// Construct an PPC ELF object writer.
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std::unique_ptr<MCObjectTargetWriter> createPPCELFObjectWriter(bool Is64Bit,
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uint8_t OSABI);
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/// Construct a PPC Mach-O object writer.
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std::unique_ptr<MCObjectTargetWriter>
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createPPCMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype);
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/// Construct a PPC XCOFF object writer.
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std::unique_ptr<MCObjectTargetWriter> createPPCXCOFFObjectWriter(bool Is64Bit);
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/// Returns true iff Val consists of one contiguous run of 1s with any number of
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/// 0s on either side. The 1s are allowed to wrap from LSB to MSB, so
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/// 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is not,
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/// since all 1s are not contiguous.
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static inline bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
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if (!Val)
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return false;
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if (isShiftedMask_32(Val)) {
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// look for the first non-zero bit
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MB = countLeadingZeros(Val);
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// look for the first zero bit after the run of ones
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ME = countLeadingZeros((Val - 1) ^ Val);
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return true;
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} else {
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Val = ~Val; // invert mask
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if (isShiftedMask_32(Val)) {
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// effectively look for the first zero bit
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ME = countLeadingZeros(Val) - 1;
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// effectively look for the first one bit after the run of zeros
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MB = countLeadingZeros((Val - 1) ^ Val) + 1;
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return true;
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}
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}
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// no run present
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return false;
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}
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static inline bool isRunOfOnes64(uint64_t Val, unsigned &MB, unsigned &ME) {
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if (!Val)
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return false;
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if (isShiftedMask_64(Val)) {
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// look for the first non-zero bit
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MB = countLeadingZeros(Val);
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// look for the first zero bit after the run of ones
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ME = countLeadingZeros((Val - 1) ^ Val);
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return true;
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} else {
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Val = ~Val; // invert mask
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if (isShiftedMask_64(Val)) {
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// effectively look for the first zero bit
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ME = countLeadingZeros(Val) - 1;
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// effectively look for the first one bit after the run of zeros
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MB = countLeadingZeros((Val - 1) ^ Val) + 1;
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return true;
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}
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}
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// no run present
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return false;
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}
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} // end namespace llvm
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// Generated files will use "namespace PPC". To avoid symbol clash,
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// undefine PPC here. PPC may be predefined on some hosts.
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#undef PPC
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// Defines symbolic names for PowerPC registers. This defines a mapping from
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// register name to register number.
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//
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#define GET_REGINFO_ENUM
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#include "PPCGenRegisterInfo.inc"
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// Defines symbolic names for the PowerPC instructions.
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//
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#define GET_INSTRINFO_ENUM
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#define GET_INSTRINFO_SCHED_ENUM
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#define GET_INSTRINFO_MC_HELPER_DECLS
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#include "PPCGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "PPCGenSubtargetInfo.inc"
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#define PPC_REGS0_7(X) \
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{ \
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X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
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}
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#define PPC_REGS0_31(X) \
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{ \
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X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
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X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
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X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
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}
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#define PPC_REGS0_63(X) \
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{ \
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X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
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X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
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X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31, \
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X##32, X##33, X##34, X##35, X##36, X##37, X##38, X##39, X##40, X##41, \
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X##42, X##43, X##44, X##45, X##46, X##47, X##48, X##49, X##50, X##51, \
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X##52, X##53, X##54, X##55, X##56, X##57, X##58, X##59, X##60, X##61, \
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X##62, X##63 \
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}
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#define PPC_REGS_NO0_31(Z, X) \
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{ \
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Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
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X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
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X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
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}
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#define PPC_REGS_LO_HI(LO, HI) \
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{ \
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LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, LO##9, \
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LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, LO##16, LO##17, \
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LO##18, LO##19, LO##20, LO##21, LO##22, LO##23, LO##24, LO##25, \
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LO##26, LO##27, LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \
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HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, HI##10, HI##11, \
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HI##12, HI##13, HI##14, HI##15, HI##16, HI##17, HI##18, HI##19, \
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HI##20, HI##21, HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \
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HI##28, HI##29, HI##30, HI##31 \
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}
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#define PPC_REGS0_7(X) \
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{ \
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X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
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}
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#define PPC_REGS0_3(X) \
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{ \
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X##0, X##1, X##2, X##3 \
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}
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using llvm::MCPhysReg;
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#define DEFINE_PPC_REGCLASSES \
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static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
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static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
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static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
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static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \
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static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
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static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \
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static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
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static const MCPhysReg RRegsNoR0[32] = \
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PPC_REGS_NO0_31(PPC::ZERO, PPC::R); \
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static const MCPhysReg XRegsNoX0[32] = \
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PPC_REGS_NO0_31(PPC::ZERO8, PPC::X); \
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static const MCPhysReg VSRegs[64] = \
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PPC_REGS_LO_HI(PPC::VSL, PPC::V); \
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static const MCPhysReg VSFRegs[64] = \
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PPC_REGS_LO_HI(PPC::F, PPC::VF); \
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static const MCPhysReg VSSRegs[64] = \
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PPC_REGS_LO_HI(PPC::F, PPC::VF); \
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static const MCPhysReg CRBITRegs[32] = { \
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PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, \
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PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, \
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PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, \
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PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, \
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PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, \
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PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, \
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PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, \
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PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN}; \
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static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC::CR); \
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static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC::ACC); \
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static const MCPhysReg WACCRegs[8] = PPC_REGS0_7(PPC::WACC); \
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static const MCPhysReg WACC_HIRegs[8] = PPC_REGS0_7(PPC::WACC_HI); \
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static const MCPhysReg DMRROWpRegs[32] = PPC_REGS0_31(PPC::DMRROWp); \
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static const MCPhysReg DMRROWRegs[64] = PPC_REGS0_63(PPC::DMRROW); \
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static const MCPhysReg DMRRegs[8] = PPC_REGS0_7(PPC::DMR); \
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static const MCPhysReg DMRpRegs[4] = PPC_REGS0_3(PPC::DMRp);
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#endif // LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
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