70a5d8e4c4
clang (like gcc) has the -mtune= command line option. This option adds the "tune-cpu" attribute to a function. The intended functionality is that the scheduling model of that cpu is used. E.g. -mtune=pwr9 -march=pwr8 generates only instructions supported on pwr8 but uses the scheduling model of pwr9 for it. This PR adds the infrastructure to support this in LLVM. clang support was added in https://reviews.llvm.org/D130526. Reviewed By: amyk, qiucf Differential Revision: https://reviews.llvm.org/D138317
306 lines
9.5 KiB
C++
306 lines
9.5 KiB
C++
//===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the PowerPC specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
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#define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
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#include "PPCFrameLowering.h"
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#include "PPCISelLowering.h"
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#include "PPCInstrInfo.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/RegisterBankInfo.h"
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "PPCGenSubtargetInfo.inc"
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// GCC #defines PPC on Linux but we use it as our namespace name
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#undef PPC
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namespace llvm {
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class StringRef;
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namespace PPC {
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// -m directive values.
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enum {
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DIR_NONE,
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DIR_32,
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DIR_440,
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DIR_601,
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DIR_602,
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DIR_603,
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DIR_7400,
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DIR_750,
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DIR_970,
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DIR_A2,
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DIR_E500,
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DIR_E500mc,
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DIR_E5500,
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DIR_PWR3,
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DIR_PWR4,
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DIR_PWR5,
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DIR_PWR5X,
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DIR_PWR6,
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DIR_PWR6X,
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DIR_PWR7,
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DIR_PWR8,
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DIR_PWR9,
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DIR_PWR10,
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DIR_PWR_FUTURE,
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DIR_64
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};
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}
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class GlobalValue;
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class PPCSubtarget : public PPCGenSubtargetInfo {
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public:
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enum POPCNTDKind {
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POPCNTD_Unavailable,
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POPCNTD_Slow,
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POPCNTD_Fast
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};
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protected:
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/// TargetTriple - What processor and OS we're targeting.
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Triple TargetTriple;
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/// stackAlignment - The minimum alignment known to hold of the stack frame on
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/// entry to the function and which must be maintained by every function.
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Align StackAlignment;
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/// Selected instruction itineraries (one entry per itinerary class.)
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InstrItineraryData InstrItins;
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// Bool members corresponding to the SubtargetFeatures defined in tablegen.
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#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
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bool ATTRIBUTE = DEFAULT;
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#include "PPCGenSubtargetInfo.inc"
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/// Which cpu directive was used.
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unsigned CPUDirective;
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bool IsPPC64;
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bool IsLittleEndian;
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POPCNTDKind HasPOPCNTD;
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const PPCTargetMachine &TM;
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PPCFrameLowering FrameLowering;
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PPCInstrInfo InstrInfo;
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PPCTargetLowering TLInfo;
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SelectionDAGTargetInfo TSInfo;
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/// GlobalISel related APIs.
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std::unique_ptr<CallLowering> CallLoweringInfo;
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std::unique_ptr<LegalizerInfo> Legalizer;
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std::unique_ptr<RegisterBankInfo> RegBankInfo;
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std::unique_ptr<InstructionSelector> InstSelector;
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public:
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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///
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PPCSubtarget(const Triple &TT, const std::string &CPU,
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const std::string &TuneCPU, const std::string &FS,
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const PPCTargetMachine &TM);
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
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/// getStackAlignment - Returns the minimum alignment known to hold of the
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/// stack frame on entry to the function and which must be maintained by every
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/// function for this subtarget.
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Align getStackAlignment() const { return StackAlignment; }
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/// getCPUDirective - Returns the -m directive specified for the cpu.
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///
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unsigned getCPUDirective() const { return CPUDirective; }
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/// getInstrItins - Return the instruction itineraries based on subtarget
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/// selection.
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const InstrItineraryData *getInstrItineraryData() const override {
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return &InstrItins;
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}
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const PPCFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const PPCTargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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const PPCRegisterInfo *getRegisterInfo() const override {
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return &getInstrInfo()->getRegisterInfo();
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}
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const PPCTargetMachine &getTargetMachine() const { return TM; }
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/// initializeSubtargetDependencies - Initializes using a CPU, a TuneCPU, and
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/// feature string so that we can use initializer lists for subtarget
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/// initialization.
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PPCSubtarget &initializeSubtargetDependencies(StringRef CPU,
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StringRef TuneCPU,
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StringRef FS);
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private:
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void initializeEnvironment();
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void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
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public:
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/// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
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///
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bool isPPC64() const;
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// useSoftFloat - Return true if soft-float option is turned on.
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bool useSoftFloat() const {
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if (isAIXABI() && !HasHardFloat)
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report_fatal_error("soft-float is not yet supported on AIX.");
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return !HasHardFloat;
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}
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// isLittleEndian - True if generating little-endian code
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bool isLittleEndian() const { return IsLittleEndian; }
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// Getters for SubtargetFeatures defined in tablegen.
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#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
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bool GETTER() const { return ATTRIBUTE; }
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#include "PPCGenSubtargetInfo.inc"
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Align getPlatformStackAlignment() const {
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return Align(16);
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}
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unsigned getRedZoneSize() const {
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if (isPPC64())
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// 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
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return 288;
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// AIX PPC32: 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
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// PPC32 SVR4ABI has no redzone.
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return isAIXABI() ? 220 : 0;
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}
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bool needsSwapsForVSXMemOps() const {
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return hasVSX() && isLittleEndian() && !hasP9Vector();
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}
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POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
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const Triple &getTargetTriple() const { return TargetTriple; }
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bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
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bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
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bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
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bool isAIXABI() const { return TargetTriple.isOSAIX(); }
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bool isSVR4ABI() const { return !isAIXABI(); }
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bool isELFv2ABI() const;
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bool is64BitELFABI() const { return isSVR4ABI() && isPPC64(); }
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bool is32BitELFABI() const { return isSVR4ABI() && !isPPC64(); }
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bool isUsingPCRelativeCalls() const;
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/// Originally, this function return hasISEL(). Now we always enable it,
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/// but may expand the ISEL instruction later.
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bool enableEarlyIfConversion() const override { return true; }
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/// Scheduling customization.
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bool enableMachineScheduler() const override;
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/// Pipeliner customization.
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bool enableMachinePipeliner() const override;
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/// Machine Pipeliner customization
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bool useDFAforSMS() const override;
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/// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
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bool enablePostRAScheduler() const override;
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AntiDepBreakMode getAntiDepBreakMode() const override;
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void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
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void overrideSchedPolicy(MachineSchedPolicy &Policy,
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unsigned NumRegionInstrs) const override;
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bool useAA() const override;
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bool enableSubRegLiveness() const override;
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/// True if the GV will be accessed via an indirect symbol.
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bool isGVIndirectSymbol(const GlobalValue *GV) const;
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/// True if the ABI is descriptor based.
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bool usesFunctionDescriptors() const {
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// Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
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// v1 ABI uses descriptors.
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return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
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}
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unsigned descriptorTOCAnchorOffset() const {
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assert(usesFunctionDescriptors() &&
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"Should only be called when the target uses descriptors.");
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return IsPPC64 ? 8 : 4;
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}
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unsigned descriptorEnvironmentPointerOffset() const {
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assert(usesFunctionDescriptors() &&
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"Should only be called when the target uses descriptors.");
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return IsPPC64 ? 16 : 8;
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}
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MCRegister getEnvironmentPointerRegister() const {
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assert(usesFunctionDescriptors() &&
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"Should only be called when the target uses descriptors.");
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return IsPPC64 ? PPC::X11 : PPC::R11;
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}
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MCRegister getTOCPointerRegister() const {
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assert((is64BitELFABI() || isAIXABI()) &&
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"Should only be called when the target is a TOC based ABI.");
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return IsPPC64 ? PPC::X2 : PPC::R2;
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}
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MCRegister getStackPointerRegister() const {
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return IsPPC64 ? PPC::X1 : PPC::R1;
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}
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bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
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bool isPredictableSelectIsExpensive() const {
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return PredictableSelectIsExpensive;
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}
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// Select allocation orders of GPRC and G8RC. It should be strictly consistent
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// with corresponding AltOrders in PPCRegisterInfo.td.
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unsigned getGPRAllocationOrderIdx() const {
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if (is64BitELFABI())
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return 1;
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if (isAIXABI())
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return 2;
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return 0;
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}
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// GlobalISEL
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const CallLowering *getCallLowering() const override;
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const RegisterBankInfo *getRegBankInfo() const override;
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const LegalizerInfo *getLegalizerInfo() const override;
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InstructionSelector *getInstructionSelector() const override;
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};
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} // End llvm namespace
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#endif
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