98e342dca2
On x86 and AArch, SIMD instructions encode all of the scheduling information in the instruction itself. For example, VADD.I16 q0, q1, q2 is a neon instruction that operates on 16-bit integer elements stored in 128-bit Q registers, which leads to eight 16-bit lanes in parallel. This kind of information impacts how the instruction takes to execute and what dependencies this may cause. On RISCV however, the data that impacts scheduling is encoded in CSR registers such as vtype or vl, in addition with the instruction itself. But MCA does not track or use the data in these registers. This patch fixes this problem by introducing Instruments into MCA. * Replace `CodeRegions` with `AnalysisRegions` * Add `Instrument` and `InstrumentManager` * Add `InstrumentRegions` * Add RISCV Instrument and `InstrumentManager` * Parse `Instruments` in driver * Use instruments to override schedule class * RISCV use lmul instrument to override schedule class * Fix unit tests to pass empty instruments * Add -ignore-im clopt to disable this change A prior version of this patch was commited in5e82ee5373.2323a4ee61reverted that change because the unit test files caused build errors. The change with fixes were committed inb88b8307bfbut reverted once againe8e92c8313due to more build errors. This commit adds the prior changes and fixes the build error. Differential Revision: https://reviews.llvm.org/D137440
63 lines
2.1 KiB
C++
63 lines
2.1 KiB
C++
//===-------------------- RISCVCustomBehaviour.h -----------------*-C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file defines the RISCVCustomBehaviour class which inherits from
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/// CustomBehaviour. This class is used by the tool llvm-mca to enforce
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/// target specific behaviour that is not expressed well enough in the
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/// scheduling model for mca to enforce it automatically.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MCA_RISCVCUSTOMBEHAVIOUR_H
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#define LLVM_LIB_TARGET_RISCV_MCA_RISCVCUSTOMBEHAVIOUR_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MCA/CustomBehaviour.h"
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namespace llvm {
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namespace mca {
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class RISCVLMULInstrument : public Instrument {
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public:
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static const StringRef DESC_NAME;
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static bool isDataValid(StringRef Data);
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RISCVLMULInstrument(StringRef Data) : Instrument(DESC_NAME, Data) {}
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~RISCVLMULInstrument() = default;
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uint8_t getLMUL() const;
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};
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class RISCVInstrumentManager : public InstrumentManager {
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public:
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RISCVInstrumentManager(const MCSubtargetInfo &STI, const MCInstrInfo &MCII)
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: InstrumentManager(STI, MCII) {}
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bool shouldIgnoreInstruments() const override { return false; }
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bool supportsInstrumentType(StringRef Type) const override;
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/// Create a Instrument for RISCV target
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SharedInstrument createInstrument(StringRef Desc, StringRef Data) override;
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/// Using the Instrument, returns a SchedClassID to use instead of
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/// the SchedClassID that belongs to the MCI or the original SchedClassID.
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unsigned
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getSchedClassID(const MCInstrInfo &MCII, const MCInst &MCI,
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const SmallVector<SharedInstrument> &IVec) const override;
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};
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} // namespace mca
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} // namespace llvm
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#endif
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