da7415acda
sifive-7-series can predicate ALU instructions in the shadow of a branch not just move instructions. This patch implements analyzeSelect/optimizeSelect to predicate these operations. This is based on ARM's implementation which can predicate using flags and condition codes. I've restricted it to just the instructions we have test cases for, but it can be extended in the future. Reviewed By: reames Differential Revision: https://reviews.llvm.org/D140053
403 lines
14 KiB
C++
403 lines
14 KiB
C++
//===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that expands pseudo instructions into target
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// instructions. This pass should be run after register allocation but before
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// the post-regalloc scheduling pass.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVInstrInfo.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/MC/MCContext.h"
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using namespace llvm;
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#define RISCV_EXPAND_PSEUDO_NAME "RISCV pseudo instruction expansion pass"
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#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISCV Pre-RA pseudo instruction expansion pass"
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namespace {
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class RISCVExpandPseudo : public MachineFunctionPass {
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public:
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const RISCVInstrInfo *TII;
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static char ID;
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RISCVExpandPseudo() : MachineFunctionPass(ID) {
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initializeRISCVExpandPseudoPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
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private:
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bool expandMBB(MachineBasicBlock &MBB);
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bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandVSetVL(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
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bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, unsigned Opcode);
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};
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char RISCVExpandPseudo::ID = 0;
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bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
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TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
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bool Modified = false;
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for (auto &MBB : MF)
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Modified |= expandMBB(MBB);
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return Modified;
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}
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bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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Modified |= expandMI(MBB, MBBI, NMBBI);
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MBBI = NMBBI;
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}
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return Modified;
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}
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bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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// RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
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// expanded instructions for each pseudo is correct in the Size field of the
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// tablegen definition for the pseudo.
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switch (MBBI->getOpcode()) {
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case RISCV::PseudoCCMOVGPR:
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case RISCV::PseudoCCADD:
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case RISCV::PseudoCCSUB:
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case RISCV::PseudoCCAND:
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case RISCV::PseudoCCOR:
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case RISCV::PseudoCCXOR:
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case RISCV::PseudoCCADDW:
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case RISCV::PseudoCCSUBW:
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return expandCCOp(MBB, MBBI, NextMBBI);
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case RISCV::PseudoVSETVLI:
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case RISCV::PseudoVSETVLIX0:
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case RISCV::PseudoVSETIVLI:
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return expandVSetVL(MBB, MBBI);
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case RISCV::PseudoVMCLR_M_B1:
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case RISCV::PseudoVMCLR_M_B2:
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case RISCV::PseudoVMCLR_M_B4:
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case RISCV::PseudoVMCLR_M_B8:
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case RISCV::PseudoVMCLR_M_B16:
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case RISCV::PseudoVMCLR_M_B32:
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case RISCV::PseudoVMCLR_M_B64:
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// vmclr.m vd => vmxor.mm vd, vd, vd
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return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);
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case RISCV::PseudoVMSET_M_B1:
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case RISCV::PseudoVMSET_M_B2:
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case RISCV::PseudoVMSET_M_B4:
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case RISCV::PseudoVMSET_M_B8:
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case RISCV::PseudoVMSET_M_B16:
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case RISCV::PseudoVMSET_M_B32:
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case RISCV::PseudoVMSET_M_B64:
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// vmset.m vd => vmxnor.mm vd, vd, vd
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return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
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}
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return false;
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}
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bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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MachineFunction *MF = MBB.getParent();
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
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MachineBasicBlock *MergeBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
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MF->insert(++MBB.getIterator(), TrueBB);
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MF->insert(++TrueBB->getIterator(), MergeBB);
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// We want to copy the "true" value when the condition is true which means
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// we need to invert the branch condition to jump over TrueBB when the
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// condition is false.
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auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
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CC = RISCVCC::getOppositeBranchCondition(CC);
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// Insert branch instruction.
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BuildMI(MBB, MBBI, DL, TII->getBrCond(CC))
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.addReg(MI.getOperand(1).getReg())
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.addReg(MI.getOperand(2).getReg())
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.addMBB(MergeBB);
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Register DestReg = MI.getOperand(0).getReg();
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assert(MI.getOperand(4).getReg() == DestReg);
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if (MI.getOpcode() == RISCV::PseudoCCMOVGPR) {
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// Add MV.
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BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg)
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.add(MI.getOperand(5))
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.addImm(0);
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} else {
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unsigned NewOpc;
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switch (MI.getOpcode()) {
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default:
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llvm_unreachable("Unexpected opcode!");
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case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
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case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
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case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
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case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
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case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
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case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
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case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
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}
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BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
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.add(MI.getOperand(5))
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.add(MI.getOperand(6));
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}
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TrueBB->addSuccessor(MergeBB);
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MergeBB->splice(MergeBB->end(), &MBB, MI, MBB.end());
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MergeBB->transferSuccessors(&MBB);
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MBB.addSuccessor(TrueBB);
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MBB.addSuccessor(MergeBB);
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NextMBBI = MBB.end();
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MI.eraseFromParent();
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// Make sure live-ins are correctly attached to this new basic block.
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LivePhysRegs LiveRegs;
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computeAndAddLiveIns(LiveRegs, *TrueBB);
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computeAndAddLiveIns(LiveRegs, *MergeBB);
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return true;
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}
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bool RISCVExpandPseudo::expandVSetVL(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) {
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assert(MBBI->getNumExplicitOperands() == 3 && MBBI->getNumOperands() >= 5 &&
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"Unexpected instruction format");
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DebugLoc DL = MBBI->getDebugLoc();
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assert((MBBI->getOpcode() == RISCV::PseudoVSETVLI ||
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MBBI->getOpcode() == RISCV::PseudoVSETVLIX0 ||
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MBBI->getOpcode() == RISCV::PseudoVSETIVLI) &&
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"Unexpected pseudo instruction");
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unsigned Opcode;
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if (MBBI->getOpcode() == RISCV::PseudoVSETIVLI)
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Opcode = RISCV::VSETIVLI;
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else
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Opcode = RISCV::VSETVLI;
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const MCInstrDesc &Desc = TII->get(Opcode);
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assert(Desc.getNumOperands() == 3 && "Unexpected instruction format");
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Register DstReg = MBBI->getOperand(0).getReg();
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bool DstIsDead = MBBI->getOperand(0).isDead();
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BuildMI(MBB, MBBI, DL, Desc)
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.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
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.add(MBBI->getOperand(1)) // VL
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.add(MBBI->getOperand(2)); // VType
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MBBI->eraseFromParent(); // The pseudo instruction is gone now.
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return true;
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}
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bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned Opcode) {
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DebugLoc DL = MBBI->getDebugLoc();
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Register DstReg = MBBI->getOperand(0).getReg();
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const MCInstrDesc &Desc = TII->get(Opcode);
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BuildMI(MBB, MBBI, DL, Desc, DstReg)
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.addReg(DstReg, RegState::Undef)
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.addReg(DstReg, RegState::Undef);
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MBBI->eraseFromParent(); // The pseudo instruction is gone now.
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return true;
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}
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class RISCVPreRAExpandPseudo : public MachineFunctionPass {
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public:
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const RISCVInstrInfo *TII;
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static char ID;
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RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {
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initializeRISCVPreRAExpandPseudoPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override {
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return RISCV_PRERA_EXPAND_PSEUDO_NAME;
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}
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private:
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bool expandMBB(MachineBasicBlock &MBB);
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bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandAuipcInstPair(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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unsigned FlagsHi, unsigned SecondOpcode);
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bool expandLoadLocalAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandLoadAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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};
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char RISCVPreRAExpandPseudo::ID = 0;
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bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
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TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
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bool Modified = false;
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for (auto &MBB : MF)
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Modified |= expandMBB(MBB);
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return Modified;
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}
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bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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Modified |= expandMI(MBB, MBBI, NMBBI);
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MBBI = NMBBI;
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}
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return Modified;
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}
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bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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switch (MBBI->getOpcode()) {
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case RISCV::PseudoLLA:
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return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
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case RISCV::PseudoLA:
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return expandLoadAddress(MBB, MBBI, NextMBBI);
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case RISCV::PseudoLA_TLS_IE:
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return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
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case RISCV::PseudoLA_TLS_GD:
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return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
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}
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return false;
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}
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bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
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unsigned SecondOpcode) {
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MachineFunction *MF = MBB.getParent();
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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Register DestReg = MI.getOperand(0).getReg();
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Register ScratchReg =
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MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
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MachineOperand &Symbol = MI.getOperand(1);
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Symbol.setTargetFlags(FlagsHi);
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MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi");
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MachineInstr *MIAUIPC =
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BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
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MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
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MachineInstr *SecondMI =
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BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
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.addReg(ScratchReg)
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.addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
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if (MI.hasOneMemOperand())
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SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
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MI.eraseFromParent();
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return true;
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}
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bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
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RISCV::ADDI);
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}
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bool RISCVPreRAExpandPseudo::expandLoadAddress(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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MachineFunction *MF = MBB.getParent();
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const auto &STI = MF->getSubtarget<RISCVSubtarget>();
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// When HWASAN is used and tagging of global variables is enabled
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// they should be accessed via the GOT, since the tagged address of a global
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// is incompatible with existing code models. This also applies to non-pic
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// mode.
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assert(MF->getTarget().isPositionIndependent() || STI.allowTaggedGlobals());
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unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
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return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
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SecondOpcode);
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}
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bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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MachineFunction *MF = MBB.getParent();
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const auto &STI = MF->getSubtarget<RISCVSubtarget>();
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unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
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return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
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SecondOpcode);
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}
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bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
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RISCV::ADDI);
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}
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} // end of anonymous namespace
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INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
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RISCV_EXPAND_PSEUDO_NAME, false, false)
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INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
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RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
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namespace llvm {
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FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
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FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); }
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} // end of namespace llvm
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