ac51cf1960
Move to RISCVInstrInfo since we need RISCVSubtarget now. Instead of asking if only the lower 32 bits are used we can now ask if the lower N bits are used. This will be needed by a future patch.
377 lines
12 KiB
C++
377 lines
12 KiB
C++
//===-------------- RISCVSExtWRemoval.cpp - MI sext.w Removal -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===---------------------------------------------------------------------===//
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//
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// This pass removes unneeded sext.w instructions at the MI level. Either
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// because the sign extended bits aren't consumed or because the input was
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// already sign extended by an earlier instruction.
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//
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//===---------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVMachineFunctionInfo.h"
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#include "RISCVSubtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-sextw-removal"
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STATISTIC(NumRemovedSExtW, "Number of removed sign-extensions");
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STATISTIC(NumTransformedToWInstrs,
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"Number of instructions transformed to W-ops");
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static cl::opt<bool> DisableSExtWRemoval("riscv-disable-sextw-removal",
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cl::desc("Disable removal of sext.w"),
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cl::init(false), cl::Hidden);
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namespace {
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class RISCVSExtWRemoval : public MachineFunctionPass {
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public:
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static char ID;
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RISCVSExtWRemoval() : MachineFunctionPass(ID) {
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initializeRISCVSExtWRemovalPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override { return "RISCV sext.w Removal"; }
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};
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} // end anonymous namespace
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char RISCVSExtWRemoval::ID = 0;
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INITIALIZE_PASS(RISCVSExtWRemoval, DEBUG_TYPE, "RISCV sext.w Removal", false,
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false)
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FunctionPass *llvm::createRISCVSExtWRemovalPass() {
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return new RISCVSExtWRemoval();
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}
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// This function returns true if the machine instruction always outputs a value
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// where bits 63:32 match bit 31.
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static bool isSignExtendingOpW(const MachineInstr &MI,
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const MachineRegisterInfo &MRI) {
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uint64_t TSFlags = MI.getDesc().TSFlags;
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// Instructions that can be determined from opcode are marked in tablegen.
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if (TSFlags & RISCVII::IsSignExtendingOpWMask)
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return true;
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// Special cases that require checking operands.
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switch (MI.getOpcode()) {
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// shifting right sufficiently makes the value 32-bit sign-extended
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case RISCV::SRAI:
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return MI.getOperand(2).getImm() >= 32;
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case RISCV::SRLI:
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return MI.getOperand(2).getImm() > 32;
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// The LI pattern ADDI rd, X0, imm is sign extended.
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case RISCV::ADDI:
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return MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0;
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// An ANDI with an 11 bit immediate will zero bits 63:11.
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case RISCV::ANDI:
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return isUInt<11>(MI.getOperand(2).getImm());
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// An ORI with an >11 bit immediate (negative 12-bit) will set bits 63:11.
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case RISCV::ORI:
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return !isUInt<11>(MI.getOperand(2).getImm());
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// Copying from X0 produces zero.
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case RISCV::COPY:
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return MI.getOperand(1).getReg() == RISCV::X0;
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}
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return false;
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}
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static bool isSignExtendedW(Register SrcReg, const MachineRegisterInfo &MRI,
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const RISCVInstrInfo &TII,
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SmallPtrSetImpl<MachineInstr *> &FixableDef) {
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SmallPtrSet<const MachineInstr *, 4> Visited;
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SmallVector<MachineInstr *, 4> Worklist;
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auto AddRegDefToWorkList = [&](Register SrcReg) {
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if (!SrcReg.isVirtual())
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return false;
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MachineInstr *SrcMI = MRI.getVRegDef(SrcReg);
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if (!SrcMI)
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return false;
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// Add SrcMI to the worklist.
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Worklist.push_back(SrcMI);
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return true;
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};
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if (!AddRegDefToWorkList(SrcReg))
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return false;
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while (!Worklist.empty()) {
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MachineInstr *MI = Worklist.pop_back_val();
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// If we already visited this instruction, we don't need to check it again.
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if (!Visited.insert(MI).second)
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continue;
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// If this is a sign extending operation we don't need to look any further.
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if (isSignExtendingOpW(*MI, MRI))
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continue;
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// Is this an instruction that propagates sign extend?
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switch (MI->getOpcode()) {
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default:
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// Unknown opcode, give up.
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return false;
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case RISCV::COPY: {
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const MachineFunction *MF = MI->getMF();
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const RISCVMachineFunctionInfo *RVFI =
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MF->getInfo<RISCVMachineFunctionInfo>();
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// If this is the entry block and the register is livein, see if we know
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// it is sign extended.
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if (MI->getParent() == &MF->front()) {
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Register VReg = MI->getOperand(0).getReg();
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if (MF->getRegInfo().isLiveIn(VReg) && RVFI->isSExt32Register(VReg))
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continue;
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}
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Register CopySrcReg = MI->getOperand(1).getReg();
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if (CopySrcReg == RISCV::X10) {
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// For a method return value, we check the ZExt/SExt flags in attribute.
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// We assume the following code sequence for method call.
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// PseudoCALL @bar, ...
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// ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
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// %0:gpr = COPY $x10
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//
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// We use the PseudoCall to look up the IR function being called to find
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// its return attributes.
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const MachineBasicBlock *MBB = MI->getParent();
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auto II = MI->getIterator();
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if (II == MBB->instr_begin() ||
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(--II)->getOpcode() != RISCV::ADJCALLSTACKUP)
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return false;
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const MachineInstr &CallMI = *(--II);
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if (!CallMI.isCall() || !CallMI.getOperand(0).isGlobal())
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return false;
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auto *CalleeFn =
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dyn_cast_if_present<Function>(CallMI.getOperand(0).getGlobal());
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if (!CalleeFn)
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return false;
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auto *IntTy = dyn_cast<IntegerType>(CalleeFn->getReturnType());
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if (!IntTy)
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return false;
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const AttributeSet &Attrs = CalleeFn->getAttributes().getRetAttrs();
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unsigned BitWidth = IntTy->getBitWidth();
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return (BitWidth <= 32 && Attrs.hasAttribute(Attribute::SExt)) ||
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(BitWidth < 32 && Attrs.hasAttribute(Attribute::ZExt));
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}
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if (!AddRegDefToWorkList(CopySrcReg))
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return false;
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break;
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}
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// For these, we just need to check if the 1st operand is sign extended.
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case RISCV::BCLRI:
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case RISCV::BINVI:
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case RISCV::BSETI:
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if (MI->getOperand(2).getImm() >= 31)
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return false;
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[[fallthrough]];
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case RISCV::REM:
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case RISCV::ANDI:
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case RISCV::ORI:
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case RISCV::XORI:
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// |Remainder| is always <= |Dividend|. If D is 32-bit, then so is R.
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// DIV doesn't work because of the edge case 0xf..f 8000 0000 / (long)-1
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// Logical operations use a sign extended 12-bit immediate.
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if (!AddRegDefToWorkList(MI->getOperand(1).getReg()))
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return false;
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break;
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case RISCV::PseudoCCADDW:
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case RISCV::PseudoCCSUBW:
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// Returns operand 4 or an ADDW/SUBW of operands 5 and 6. We only need to
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// check if operand 4 is sign extended.
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if (!AddRegDefToWorkList(MI->getOperand(4).getReg()))
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return false;
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break;
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case RISCV::REMU:
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case RISCV::AND:
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case RISCV::OR:
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case RISCV::XOR:
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case RISCV::ANDN:
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case RISCV::ORN:
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case RISCV::XNOR:
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case RISCV::MAX:
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case RISCV::MAXU:
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case RISCV::MIN:
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case RISCV::MINU:
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case RISCV::PseudoCCMOVGPR:
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case RISCV::PseudoCCAND:
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case RISCV::PseudoCCOR:
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case RISCV::PseudoCCXOR:
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case RISCV::PHI: {
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// If all incoming values are sign-extended, the output of AND, OR, XOR,
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// MIN, MAX, or PHI is also sign-extended.
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// The input registers for PHI are operand 1, 3, ...
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// The input registers for PseudoCCMOVGPR are 4 and 5.
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// The input registers for PseudoCCAND/OR/XOR are 4, 5, and 6.
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// The input registers for others are operand 1 and 2.
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unsigned B = 1, E = 3, D = 1;
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switch (MI->getOpcode()) {
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case RISCV::PHI:
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E = MI->getNumOperands();
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D = 2;
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break;
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case RISCV::PseudoCCMOVGPR:
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B = 4;
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E = 6;
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break;
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case RISCV::PseudoCCAND:
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case RISCV::PseudoCCOR:
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case RISCV::PseudoCCXOR:
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B = 4;
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E = 7;
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break;
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}
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for (unsigned I = B; I != E; I += D) {
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if (!MI->getOperand(I).isReg())
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return false;
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if (!AddRegDefToWorkList(MI->getOperand(I).getReg()))
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return false;
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}
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break;
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}
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case RISCV::VT_MASKC:
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case RISCV::VT_MASKCN:
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// Instructions return zero or operand 1. Result is sign extended if
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// operand 1 is sign extended.
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if (!AddRegDefToWorkList(MI->getOperand(1).getReg()))
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return false;
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break;
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// With these opcode, we can "fix" them with the W-version
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// if we know all users of the result only rely on bits 31:0
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case RISCV::SLLI:
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// SLLIW reads the lowest 5 bits, while SLLI reads lowest 6 bits
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if (MI->getOperand(2).getImm() >= 32)
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return false;
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[[fallthrough]];
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case RISCV::ADDI:
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case RISCV::ADD:
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case RISCV::LD:
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case RISCV::LWU:
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case RISCV::MUL:
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case RISCV::SUB:
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if (TII.hasAllWUsers(*MI, MRI)) {
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FixableDef.insert(MI);
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break;
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}
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return false;
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}
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}
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// If we get here, then every node we visited produces a sign extended value
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// or propagated sign extended values. So the result must be sign extended.
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return true;
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}
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static unsigned getWOp(unsigned Opcode) {
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switch (Opcode) {
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case RISCV::ADDI:
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return RISCV::ADDIW;
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case RISCV::ADD:
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return RISCV::ADDW;
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case RISCV::LD:
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case RISCV::LWU:
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return RISCV::LW;
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case RISCV::MUL:
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return RISCV::MULW;
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case RISCV::SLLI:
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return RISCV::SLLIW;
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case RISCV::SUB:
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return RISCV::SUBW;
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default:
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llvm_unreachable("Unexpected opcode for replacement with W variant");
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}
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}
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bool RISCVSExtWRemoval::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()) || DisableSExtWRemoval)
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return false;
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
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const RISCVInstrInfo &TII = *ST.getInstrInfo();
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if (!ST.is64Bit())
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return false;
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bool MadeChange = false;
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for (MachineBasicBlock &MBB : MF) {
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for (auto I = MBB.begin(), IE = MBB.end(); I != IE;) {
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MachineInstr *MI = &*I++;
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// We're looking for the sext.w pattern ADDIW rd, rs1, 0.
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if (!RISCV::isSEXT_W(*MI))
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continue;
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Register SrcReg = MI->getOperand(1).getReg();
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SmallPtrSet<MachineInstr *, 4> FixableDefs;
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// If all users only use the lower bits, this sext.w is redundant.
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// Or if all definitions reaching MI sign-extend their output,
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// then sext.w is redundant.
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if (!TII.hasAllWUsers(*MI, MRI) &&
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!isSignExtendedW(SrcReg, MRI, TII, FixableDefs))
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continue;
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Register DstReg = MI->getOperand(0).getReg();
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if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg)))
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continue;
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// Convert Fixable instructions to their W versions.
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for (MachineInstr *Fixable : FixableDefs) {
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LLVM_DEBUG(dbgs() << "Replacing " << *Fixable);
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Fixable->setDesc(TII.get(getWOp(Fixable->getOpcode())));
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Fixable->clearFlag(MachineInstr::MIFlag::NoSWrap);
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Fixable->clearFlag(MachineInstr::MIFlag::NoUWrap);
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Fixable->clearFlag(MachineInstr::MIFlag::IsExact);
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LLVM_DEBUG(dbgs() << " with " << *Fixable);
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++NumTransformedToWInstrs;
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}
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LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
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MRI.replaceRegWith(DstReg, SrcReg);
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MRI.clearKillFlags(SrcReg);
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MI->eraseFromParent();
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++NumRemovedSExtW;
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MadeChange = true;
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}
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}
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return MadeChange;
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}
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