3e0bf1c7a9
D25618 added a method to verify the instruction predicates for an emitted instruction, through verifyInstructionPredicates added into <Target>MCCodeEmitter::encodeInstruction. This is a very useful idea, but the implementation inside MCCodeEmitter made it only fire for object files, not assembly which most of the llvm test suite uses. This patch moves the code into the <Target>_MC::verifyInstructionPredicates method, inside the InstrInfo. The allows it to be called from other places, such as in this patch where it is called from the <Target>AsmPrinter::emitInstruction methods which should trigger for both assembly and object files. It can also be called from other places such as verifyInstruction, but that is not done here (it tends to catch errors earlier, but in reality just shows all the mir tests that have incorrect feature predicates). The interface was also simplified slightly, moving computeAvailableFeatures into the function so that it does not need to be called externally. The ARM, AMDGPU (but not R600), AVR, Mips and X86 backends all currently show errors in the test-suite, so have been disabled with FIXME comments. Recommitted with some fixes for the leftover MCII variables in release builds. Differential Revision: https://reviews.llvm.org/D129506
423 lines
12 KiB
C++
423 lines
12 KiB
C++
//==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file provides WebAssembly-specific target descriptions.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
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#define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
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#include "../WebAssemblySubtarget.h"
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#include "llvm/BinaryFormat/Wasm.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Support/DataTypes.h"
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#include <memory>
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namespace llvm {
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCInstrInfo;
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class MCObjectTargetWriter;
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class Triple;
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MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII);
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MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT);
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std::unique_ptr<MCObjectTargetWriter>
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createWebAssemblyWasmObjectWriter(bool Is64Bit, bool IsEmscripten);
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namespace WebAssembly {
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enum OperandType {
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/// Basic block label in a branch construct.
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OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET,
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/// Local index.
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OPERAND_LOCAL,
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/// Global index.
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OPERAND_GLOBAL,
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/// 32-bit integer immediates.
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OPERAND_I32IMM,
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/// 64-bit integer immediates.
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OPERAND_I64IMM,
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/// 32-bit floating-point immediates.
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OPERAND_F32IMM,
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/// 64-bit floating-point immediates.
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OPERAND_F64IMM,
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/// 8-bit vector lane immediate
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OPERAND_VEC_I8IMM,
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/// 16-bit vector lane immediate
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OPERAND_VEC_I16IMM,
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/// 32-bit vector lane immediate
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OPERAND_VEC_I32IMM,
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/// 64-bit vector lane immediate
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OPERAND_VEC_I64IMM,
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/// 32-bit unsigned function indices.
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OPERAND_FUNCTION32,
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/// 32-bit unsigned memory offsets.
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OPERAND_OFFSET32,
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/// 64-bit unsigned memory offsets.
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OPERAND_OFFSET64,
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/// p2align immediate for load and store address alignment.
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OPERAND_P2ALIGN,
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/// signature immediate for block/loop.
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OPERAND_SIGNATURE,
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/// type signature immediate for call_indirect.
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OPERAND_TYPEINDEX,
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/// Tag index.
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OPERAND_TAG,
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/// A list of branch targets for br_list.
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OPERAND_BRLIST,
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/// 32-bit unsigned table number.
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OPERAND_TABLE,
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};
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} // end namespace WebAssembly
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namespace WebAssemblyII {
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/// Target Operand Flag enum.
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enum TOF {
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MO_NO_FLAG = 0,
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// On a symbol operand this indicates that the immediate is a wasm global
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// index. The value of the wasm global will be set to the symbol address at
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// runtime. This adds a level of indirection similar to the GOT on native
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// platforms.
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MO_GOT,
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// Same as MO_GOT but the address stored in the global is a TLS address.
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MO_GOT_TLS,
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// On a symbol operand this indicates that the immediate is the symbol
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// address relative the __memory_base wasm global.
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// Only applicable to data symbols.
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MO_MEMORY_BASE_REL,
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// On a symbol operand this indicates that the immediate is the symbol
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// address relative the __tls_base wasm global.
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// Only applicable to data symbols.
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MO_TLS_BASE_REL,
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// On a symbol operand this indicates that the immediate is the symbol
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// address relative the __table_base wasm global.
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// Only applicable to function symbols.
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MO_TABLE_BASE_REL,
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};
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} // end namespace WebAssemblyII
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} // end namespace llvm
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// Defines symbolic names for WebAssembly registers. This defines a mapping from
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// register name to register number.
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//
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#define GET_REGINFO_ENUM
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#include "WebAssemblyGenRegisterInfo.inc"
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// Defines symbolic names for the WebAssembly instructions.
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//
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#define GET_INSTRINFO_ENUM
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#define GET_INSTRINFO_MC_HELPER_DECLS
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#include "WebAssemblyGenInstrInfo.inc"
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namespace llvm {
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namespace WebAssembly {
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/// Instruction opcodes emitted via means other than CodeGen.
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static const unsigned Nop = 0x01;
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static const unsigned End = 0x0b;
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/// Return the default p2align value for a load or store with the given opcode.
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inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
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switch (Opc) {
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#define WASM_LOAD_STORE(NAME) \
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case WebAssembly::NAME##_A32: \
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case WebAssembly::NAME##_A64: \
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case WebAssembly::NAME##_A32_S: \
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case WebAssembly::NAME##_A64_S:
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WASM_LOAD_STORE(LOAD8_S_I32)
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WASM_LOAD_STORE(LOAD8_U_I32)
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WASM_LOAD_STORE(LOAD8_S_I64)
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WASM_LOAD_STORE(LOAD8_U_I64)
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WASM_LOAD_STORE(ATOMIC_LOAD8_U_I32)
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WASM_LOAD_STORE(ATOMIC_LOAD8_U_I64)
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WASM_LOAD_STORE(STORE8_I32)
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WASM_LOAD_STORE(STORE8_I64)
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WASM_LOAD_STORE(ATOMIC_STORE8_I32)
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WASM_LOAD_STORE(ATOMIC_STORE8_I64)
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WASM_LOAD_STORE(ATOMIC_RMW8_U_ADD_I32)
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WASM_LOAD_STORE(ATOMIC_RMW8_U_ADD_I64)
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WASM_LOAD_STORE(ATOMIC_RMW8_U_SUB_I32)
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WASM_LOAD_STORE(ATOMIC_RMW8_U_SUB_I64)
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WASM_LOAD_STORE(ATOMIC_RMW8_U_AND_I32)
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WASM_LOAD_STORE(ATOMIC_RMW8_U_AND_I64)
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WASM_LOAD_STORE(ATOMIC_RMW8_U_OR_I32)
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WASM_LOAD_STORE(ATOMIC_RMW8_U_OR_I64)
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WASM_LOAD_STORE(ATOMIC_RMW8_U_XOR_I32)
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WASM_LOAD_STORE(ATOMIC_RMW8_U_XOR_I64)
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WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I32)
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WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I64)
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WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I32)
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WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I64)
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WASM_LOAD_STORE(LOAD8_SPLAT)
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WASM_LOAD_STORE(LOAD_LANE_I8x16)
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WASM_LOAD_STORE(STORE_LANE_I8x16)
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return 0;
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WASM_LOAD_STORE(LOAD16_S_I32)
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WASM_LOAD_STORE(LOAD16_U_I32)
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WASM_LOAD_STORE(LOAD16_S_I64)
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WASM_LOAD_STORE(LOAD16_U_I64)
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WASM_LOAD_STORE(ATOMIC_LOAD16_U_I32)
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WASM_LOAD_STORE(ATOMIC_LOAD16_U_I64)
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WASM_LOAD_STORE(STORE16_I32)
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WASM_LOAD_STORE(STORE16_I64)
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WASM_LOAD_STORE(ATOMIC_STORE16_I32)
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WASM_LOAD_STORE(ATOMIC_STORE16_I64)
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WASM_LOAD_STORE(ATOMIC_RMW16_U_ADD_I32)
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WASM_LOAD_STORE(ATOMIC_RMW16_U_ADD_I64)
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WASM_LOAD_STORE(ATOMIC_RMW16_U_SUB_I32)
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WASM_LOAD_STORE(ATOMIC_RMW16_U_SUB_I64)
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WASM_LOAD_STORE(ATOMIC_RMW16_U_AND_I32)
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WASM_LOAD_STORE(ATOMIC_RMW16_U_AND_I64)
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WASM_LOAD_STORE(ATOMIC_RMW16_U_OR_I32)
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WASM_LOAD_STORE(ATOMIC_RMW16_U_OR_I64)
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WASM_LOAD_STORE(ATOMIC_RMW16_U_XOR_I32)
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WASM_LOAD_STORE(ATOMIC_RMW16_U_XOR_I64)
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WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I32)
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WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I64)
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WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I32)
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WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I64)
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WASM_LOAD_STORE(LOAD16_SPLAT)
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WASM_LOAD_STORE(LOAD_LANE_I16x8)
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WASM_LOAD_STORE(STORE_LANE_I16x8)
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return 1;
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WASM_LOAD_STORE(LOAD_I32)
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WASM_LOAD_STORE(LOAD_F32)
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WASM_LOAD_STORE(STORE_I32)
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WASM_LOAD_STORE(STORE_F32)
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WASM_LOAD_STORE(LOAD32_S_I64)
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WASM_LOAD_STORE(LOAD32_U_I64)
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WASM_LOAD_STORE(STORE32_I64)
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WASM_LOAD_STORE(ATOMIC_LOAD_I32)
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WASM_LOAD_STORE(ATOMIC_LOAD32_U_I64)
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WASM_LOAD_STORE(ATOMIC_STORE_I32)
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WASM_LOAD_STORE(ATOMIC_STORE32_I64)
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WASM_LOAD_STORE(ATOMIC_RMW_ADD_I32)
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WASM_LOAD_STORE(ATOMIC_RMW32_U_ADD_I64)
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WASM_LOAD_STORE(ATOMIC_RMW_SUB_I32)
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WASM_LOAD_STORE(ATOMIC_RMW32_U_SUB_I64)
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WASM_LOAD_STORE(ATOMIC_RMW_AND_I32)
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WASM_LOAD_STORE(ATOMIC_RMW32_U_AND_I64)
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WASM_LOAD_STORE(ATOMIC_RMW_OR_I32)
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WASM_LOAD_STORE(ATOMIC_RMW32_U_OR_I64)
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WASM_LOAD_STORE(ATOMIC_RMW_XOR_I32)
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WASM_LOAD_STORE(ATOMIC_RMW32_U_XOR_I64)
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WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I32)
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WASM_LOAD_STORE(ATOMIC_RMW32_U_XCHG_I64)
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WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I32)
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WASM_LOAD_STORE(ATOMIC_RMW32_U_CMPXCHG_I64)
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WASM_LOAD_STORE(MEMORY_ATOMIC_NOTIFY)
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WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT32)
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WASM_LOAD_STORE(LOAD32_SPLAT)
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WASM_LOAD_STORE(LOAD_ZERO_I32x4)
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WASM_LOAD_STORE(LOAD_LANE_I32x4)
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WASM_LOAD_STORE(STORE_LANE_I32x4)
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return 2;
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WASM_LOAD_STORE(LOAD_I64)
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WASM_LOAD_STORE(LOAD_F64)
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WASM_LOAD_STORE(STORE_I64)
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WASM_LOAD_STORE(STORE_F64)
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WASM_LOAD_STORE(ATOMIC_LOAD_I64)
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WASM_LOAD_STORE(ATOMIC_STORE_I64)
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WASM_LOAD_STORE(ATOMIC_RMW_ADD_I64)
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WASM_LOAD_STORE(ATOMIC_RMW_SUB_I64)
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WASM_LOAD_STORE(ATOMIC_RMW_AND_I64)
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WASM_LOAD_STORE(ATOMIC_RMW_OR_I64)
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WASM_LOAD_STORE(ATOMIC_RMW_XOR_I64)
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WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I64)
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WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I64)
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WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT64)
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WASM_LOAD_STORE(LOAD64_SPLAT)
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WASM_LOAD_STORE(LOAD_EXTEND_S_I16x8)
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WASM_LOAD_STORE(LOAD_EXTEND_U_I16x8)
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WASM_LOAD_STORE(LOAD_EXTEND_S_I32x4)
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WASM_LOAD_STORE(LOAD_EXTEND_U_I32x4)
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WASM_LOAD_STORE(LOAD_EXTEND_S_I64x2)
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WASM_LOAD_STORE(LOAD_EXTEND_U_I64x2)
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WASM_LOAD_STORE(LOAD_ZERO_I64x2)
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WASM_LOAD_STORE(LOAD_LANE_I64x2)
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WASM_LOAD_STORE(STORE_LANE_I64x2)
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return 3;
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WASM_LOAD_STORE(LOAD_V128)
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WASM_LOAD_STORE(STORE_V128)
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return 4;
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default:
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return -1;
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}
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#undef WASM_LOAD_STORE
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}
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inline unsigned GetDefaultP2Align(unsigned Opc) {
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auto Align = GetDefaultP2AlignAny(Opc);
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if (Align == -1U) {
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llvm_unreachable("Only loads and stores have p2align values");
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}
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return Align;
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}
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inline bool isArgument(unsigned Opc) {
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switch (Opc) {
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case WebAssembly::ARGUMENT_i32:
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case WebAssembly::ARGUMENT_i32_S:
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case WebAssembly::ARGUMENT_i64:
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case WebAssembly::ARGUMENT_i64_S:
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case WebAssembly::ARGUMENT_f32:
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case WebAssembly::ARGUMENT_f32_S:
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case WebAssembly::ARGUMENT_f64:
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case WebAssembly::ARGUMENT_f64_S:
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case WebAssembly::ARGUMENT_v16i8:
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case WebAssembly::ARGUMENT_v16i8_S:
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case WebAssembly::ARGUMENT_v8i16:
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case WebAssembly::ARGUMENT_v8i16_S:
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case WebAssembly::ARGUMENT_v4i32:
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case WebAssembly::ARGUMENT_v4i32_S:
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case WebAssembly::ARGUMENT_v2i64:
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case WebAssembly::ARGUMENT_v2i64_S:
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case WebAssembly::ARGUMENT_v4f32:
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case WebAssembly::ARGUMENT_v4f32_S:
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case WebAssembly::ARGUMENT_v2f64:
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case WebAssembly::ARGUMENT_v2f64_S:
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case WebAssembly::ARGUMENT_funcref:
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case WebAssembly::ARGUMENT_funcref_S:
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case WebAssembly::ARGUMENT_externref:
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case WebAssembly::ARGUMENT_externref_S:
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return true;
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default:
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return false;
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}
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}
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inline bool isCopy(unsigned Opc) {
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switch (Opc) {
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case WebAssembly::COPY_I32:
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case WebAssembly::COPY_I32_S:
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case WebAssembly::COPY_I64:
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case WebAssembly::COPY_I64_S:
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case WebAssembly::COPY_F32:
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case WebAssembly::COPY_F32_S:
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case WebAssembly::COPY_F64:
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case WebAssembly::COPY_F64_S:
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case WebAssembly::COPY_V128:
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case WebAssembly::COPY_V128_S:
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case WebAssembly::COPY_FUNCREF:
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case WebAssembly::COPY_FUNCREF_S:
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case WebAssembly::COPY_EXTERNREF:
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case WebAssembly::COPY_EXTERNREF_S:
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return true;
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default:
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return false;
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}
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}
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inline bool isTee(unsigned Opc) {
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switch (Opc) {
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case WebAssembly::TEE_I32:
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case WebAssembly::TEE_I32_S:
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case WebAssembly::TEE_I64:
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case WebAssembly::TEE_I64_S:
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case WebAssembly::TEE_F32:
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case WebAssembly::TEE_F32_S:
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case WebAssembly::TEE_F64:
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case WebAssembly::TEE_F64_S:
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case WebAssembly::TEE_V128:
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case WebAssembly::TEE_V128_S:
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case WebAssembly::TEE_FUNCREF:
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case WebAssembly::TEE_FUNCREF_S:
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case WebAssembly::TEE_EXTERNREF:
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case WebAssembly::TEE_EXTERNREF_S:
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return true;
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default:
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return false;
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}
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}
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inline bool isCallDirect(unsigned Opc) {
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switch (Opc) {
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case WebAssembly::CALL:
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case WebAssembly::CALL_S:
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case WebAssembly::RET_CALL:
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case WebAssembly::RET_CALL_S:
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return true;
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default:
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return false;
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}
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}
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inline bool isCallIndirect(unsigned Opc) {
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switch (Opc) {
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case WebAssembly::CALL_INDIRECT:
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case WebAssembly::CALL_INDIRECT_S:
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case WebAssembly::RET_CALL_INDIRECT:
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case WebAssembly::RET_CALL_INDIRECT_S:
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return true;
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default:
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return false;
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}
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}
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inline bool isBrTable(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case WebAssembly::BR_TABLE_I32:
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case WebAssembly::BR_TABLE_I32_S:
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case WebAssembly::BR_TABLE_I64:
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case WebAssembly::BR_TABLE_I64_S:
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return true;
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default:
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return false;
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}
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}
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inline bool isMarker(unsigned Opc) {
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switch (Opc) {
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case WebAssembly::BLOCK:
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case WebAssembly::BLOCK_S:
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case WebAssembly::END_BLOCK:
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case WebAssembly::END_BLOCK_S:
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case WebAssembly::LOOP:
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case WebAssembly::LOOP_S:
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case WebAssembly::END_LOOP:
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case WebAssembly::END_LOOP_S:
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case WebAssembly::TRY:
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case WebAssembly::TRY_S:
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case WebAssembly::END_TRY:
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case WebAssembly::END_TRY_S:
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return true;
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default:
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return false;
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}
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}
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inline bool isCatch(unsigned Opc) {
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switch (Opc) {
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case WebAssembly::CATCH:
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case WebAssembly::CATCH_S:
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case WebAssembly::CATCH_ALL:
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case WebAssembly::CATCH_ALL_S:
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return true;
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default:
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return false;
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}
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}
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} // end namespace WebAssembly
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} // end namespace llvm
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#endif
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