Files
clang-p2996/llvm/test/CodeGen/AArch64/pr55178.ll
Craig Topper 084f967370 [SelectionDAG] Constant fold (sext_inreg undef, VT) to 0 instead of undef.
The result of sign_extend_inreg needs to have as many sign bits
as requested by the VT argument. The easiest way to guarantee this
is to fold it to 0.

SystemZ test was modified to avoid using undef.

Fixes https://github.com/llvm/llvm-project/issues/55178

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D124696
2022-05-05 09:45:35 -07:00

21 lines
616 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s
; This used to generate incorrect code because we sign extended
; the undef to undef instead of to 0.
define i1 @test14(i8 %X) {
; CHECK-LABEL: test14:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-113
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: lsl w8, w8, w0
; CHECK-NEXT: sxtb w8, w8
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: cset w0, gt
; CHECK-NEXT: ret
%1 = shl i8 -113, %X
%cmp = icmp slt i8 undef, %1
ret i1 %cmp
}