690db16422
One motivation to add support for these types are the LD1Q/ST1Q instructions in SME, for which we have defined a number of load/store intrinsics which at the moment still take a `<vscale x 16 x i1>` predicate regardless of their element type. This patch adds basic support for the nxv1i1 type such that it can be passed/returned from functions, as well as some basic support to support some existing tests that result in a nxv1i1 type. It also adds support for splats. Other operations (e.g. insert/extract subvector, logical ops, etc) will be supported in follow-up patches. Reviewed By: paulwalker-arm, efriedma Differential Revision: https://reviews.llvm.org/D128665
89 lines
2.2 KiB
LLVM
89 lines
2.2 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-none-linux-gnu"
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define <vscale x 2 x i64> @test_zeroinit_2xi64() {
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; CHECK-LABEL: test_zeroinit_2xi64
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; CHECK: mov z0.d, #0
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; CHECK-NEXT: ret
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ret <vscale x 2 x i64> zeroinitializer
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}
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define <vscale x 4 x i32> @test_zeroinit_4xi32() {
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; CHECK-LABEL: test_zeroinit_4xi32
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; CHECK: mov z0.s, #0
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; CHECK-NEXT: ret
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ret <vscale x 4 x i32> zeroinitializer
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}
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define <vscale x 8 x i16> @test_zeroinit_8xi16() {
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; CHECK-LABEL: test_zeroinit_8xi16
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; CHECK: mov z0.h, #0
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; CHECK-NEXT: ret
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ret <vscale x 8 x i16> zeroinitializer
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}
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define <vscale x 16 x i8> @test_zeroinit_16xi8() {
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; CHECK-LABEL: test_zeroinit_16xi8
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; CHECK: mov z0.b, #0
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; CHECK-NEXT: ret
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ret <vscale x 16 x i8> zeroinitializer
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}
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define <vscale x 2 x double> @test_zeroinit_2xf64() {
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; CHECK-LABEL: test_zeroinit_2xf64
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; CHECK: mov z0.d, #0
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; CHECK-NEXT: ret
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ret <vscale x 2 x double> zeroinitializer
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}
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define <vscale x 4 x float> @test_zeroinit_4xf32() {
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; CHECK-LABEL: test_zeroinit_4xf32
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; CHECK: mov z0.s, #0
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; CHECK-NEXT: ret
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ret <vscale x 4 x float> zeroinitializer
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}
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define <vscale x 8 x half> @test_zeroinit_8xf16() {
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; CHECK-LABEL: test_zeroinit_8xf16
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; CHECK: mov z0.h, #0
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; CHECK-NEXT: ret
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ret <vscale x 8 x half> zeroinitializer
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}
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define <vscale x 1 x i1> @test_zeroinit_1xi1() {
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; CHECK-LABEL: test_zeroinit_1xi1
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; CHECK: pfalse p0.b
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; CHECK-NEXT: ret
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ret <vscale x 1 x i1> zeroinitializer
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}
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define <vscale x 2 x i1> @test_zeroinit_2xi1() {
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; CHECK-LABEL: test_zeroinit_2xi1
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; CHECK: pfalse p0.b
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; CHECK-NEXT: ret
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ret <vscale x 2 x i1> zeroinitializer
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}
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define <vscale x 4 x i1> @test_zeroinit_4xi1() {
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; CHECK-LABEL: test_zeroinit_4xi1
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; CHECK: pfalse p0.b
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; CHECK-NEXT: ret
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ret <vscale x 4 x i1> zeroinitializer
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}
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define <vscale x 8 x i1> @test_zeroinit_8xi1() {
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; CHECK-LABEL: test_zeroinit_8xi1
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; CHECK: pfalse p0.b
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; CHECK-NEXT: ret
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ret <vscale x 8 x i1> zeroinitializer
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}
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define <vscale x 16 x i1> @test_zeroinit_16xi1() {
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; CHECK-LABEL: test_zeroinit_16xi1
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; CHECK: pfalse p0.b
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; CHECK-NEXT: ret
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ret <vscale x 16 x i1> zeroinitializer
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}
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