18ed279a3a
Tablegen definitions for subtarget features and cpp predicate functions to access the features. New Sub-TargetProcessors and common latencies. Simple changes to MIR codegen tests which pass on gfx11 because they have the same output as previous subtargets or operate on pseudo instructions which are reused from previous subtargets. Contributors: Jay Foad <jay.foad@amd.com> Petar Avramovic <Petar.Avramovic@amd.com> Patch 4/N for upstreaming of AMDGPU gfx11 architecture Depends on D124538 Reviewed By: Petar.Avramovic, foad Differential Revision: https://reviews.llvm.org/D125261
55 lines
2.0 KiB
YAML
55 lines
2.0 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=si-fold-operands,dead-mi-elimination -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=si-fold-operands,dead-mi-elimination -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: fold_vgpr_to_vgpr_copy
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# GCN: %0:vreg_64 = IMPLICIT_DEF
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# GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
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# GCN-NEXT: %2:vgpr_32 = IMPLICIT_DEF
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# GCN-NEXT: DS_WRITE2_B32_gfx9 %0.sub0, killed %1, killed %2, 0, 1, 0, implicit $exec
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---
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name: fold_vgpr_to_vgpr_copy
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body: |
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bb.0:
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%0:vreg_64 = IMPLICIT_DEF
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%4:vgpr_32 = IMPLICIT_DEF
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%3:vgpr_32 = IMPLICIT_DEF
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%1:vgpr_32 = COPY %0.sub0
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%2:vgpr_32 = COPY %1
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DS_WRITE2_B32_gfx9 %2, killed %4, killed %3, 0, 1, 0, implicit $exec
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...
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# GCN-LABEL: name: fold_sgpr_to_vgpr_copy
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# GCN: %0:sreg_64 = IMPLICIT_DEF
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# GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
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# GCN-NEXT: %2:vgpr_32 = IMPLICIT_DEF
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# GCN-NEXT: %4:vgpr_32 = COPY %0.sub0
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# GCN-NEXT: DS_WRITE2_B32_gfx9 %4, killed %1, killed %2, 0, 1, 0, implicit $exec
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name: fold_sgpr_to_vgpr_copy
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body: |
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bb.0:
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%0:sreg_64 = IMPLICIT_DEF
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%4:vgpr_32 = IMPLICIT_DEF
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%3:vgpr_32 = IMPLICIT_DEF
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%1:sgpr_32 = COPY %0.sub0
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%2:vgpr_32 = COPY %1
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DS_WRITE2_B32_gfx9 %2, killed %4, killed %3, 0, 1, 0, implicit $exec
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...
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# GCN-LABEL: name: fma_sgpr_use
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: %4:vgpr_32 = nnan ninf nsz arcp contract afn reassoc V_FMA_F32_e64 2, %0.sub0, 0, 1073741824, 0, %0.sub1, 0, 0, implicit $mode, implicit $exec
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---
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name: fma_sgpr_use
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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%1:sgpr_32 = COPY %0.sub0
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%2:sgpr_32 = COPY %0.sub1
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%3:vgpr_32 = COPY %2
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%4:vgpr_32 = nnan ninf nsz arcp contract afn reassoc V_FMAC_F32_e64 2, %1, 0, 1073741824, 0, %3, 0, 0, implicit $mode, implicit $exec
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DS_WRITE2_B32_gfx9 undef %5:vgpr_32, killed %4, undef %6:vgpr_32, 0, 1, 0, implicit $exec
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...
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