3bffb1cd0e
Replace individual operands GLC, SLC, and DLC with a single cache_policy bitmask operand. This will reduce the number of operands in MIR and I hope the amount of code. These operands are mostly 0 anyway. Additional advantage that parser will accept these flags in any order unlike now. Differential Revision: https://reviews.llvm.org/D96469
25 lines
821 B
YAML
25 lines
821 B
YAML
# RUN: llc -mcpu=gfx900 -march=amdgcn -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck %s
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# If an INLINEASM statement is preceded by a vmem store of more than 8 bytes *and*
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# the INLINEASM defs the vregs holding the data-to-be-stored by that preceding store,
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# then the hazard recognizer should insert a s_nop in between them.
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...
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# GCN-LABEL: name: hazard-inlineasm
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# CHECK: FLAT_STORE_DWORDX4
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# CHECK-NEXT: S_NOP 0
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# CHECK-NEXT: INLINEASM
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---
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name: hazard-inlineasm
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body: |
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bb.0:
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FLAT_STORE_DWORDX4 $vgpr49_vgpr50, $vgpr26_vgpr27_vgpr28_vgpr29, 0, 0, implicit $exec, implicit $flat_scr
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INLINEASM &"v_mad_u64_u32 $0, $1, $2, $3, $4", 0, 2621450, def $vgpr26_vgpr27, 2818058, def dead $sgpr14_sgpr15, 589833, $sgpr12, 327689, killed $vgpr51, 2621449, $vgpr46_vgpr47
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S_ENDPGM 0
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...
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