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clang-p2996/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll
Nicolai Hähnle 52bc2e7577 [AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24 
Prefer to keep uniform (non-divergent) multiplies on the scalar ALU when
possible. This significantly improves some game cases by eliminating
v_readfirstlane instructions when the result feeds into a scalar
operation, like the address calculation for a scalar load or store.

Since isDivergent is only an approximation of whether a value is in
SGPRs, it can potentially regress some situations where a uniform value
ends up in a VGPR. These should be rare in real code, although the test
changes do contain a number of examples.

Most of the test changes are just using s_mul instead of v_mul/mad which
is generally better for both register pressure and latency (at least on
GFX10 where sgpr pressure doesn't affect occupancy and vector ALU
instructions have significantly longer latency than scalar ALU). Some
R600 tests now use MULLO_INT instead of MUL_UINT24.

GlobalISel appears to handle more scenarios in the desirable way,
although it can also be thrown off and fails to select the 24-bit
multiplies in some cases.

Alternative solution considered and rejected was to allow selecting
MUL_[UI]24 to S_MUL_I32. I've rejected this because the definition of
those SD operations works is don't-care on the most significant 8 bits,
and this fact is used in some combines via SimplifyDemandedBits.

Based on a patch by Nicolai Hähnle.

Differential Revision: https://reviews.llvm.org/D97063
2021-02-23 15:39:19 +00:00

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;RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,SIVI %s
;RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,VIPLUS,SIVI %s
;RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,VIPLUS,GFX9 %s
; GCN-LABEL: {{^}}test_interrupt:
; GCN: s_mov_b32 m0, 0
; GCN-NOT: s_mov_b32 m0
; GCN: s_sendmsg sendmsg(MSG_INTERRUPT)
define amdgpu_kernel void @test_interrupt() {
body:
call void @llvm.amdgcn.s.sendmsg(i32 1, i32 0);
ret void
}
; GCN-LABEL: {{^}}test_gs_emit:
; GCN: s_mov_b32 m0, 0
; GCN-NOT: s_mov_b32 m0
; GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT, 0)
define amdgpu_kernel void @test_gs_emit() {
body:
call void @llvm.amdgcn.s.sendmsg(i32 34, i32 0);
ret void
}
; GCN-LABEL: {{^}}test_gs_cut:
; GCN: s_mov_b32 m0, 0
; GCN-NOT: s_mov_b32 m0
; GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 1)
define amdgpu_kernel void @test_gs_cut() {
body:
call void @llvm.amdgcn.s.sendmsg(i32 274, i32 0);
ret void
}
; GCN-LABEL: {{^}}test_gs_emit_cut:
; GCN: s_mov_b32 m0, 0
; GCN-NOT: s_mov_b32 m0
; GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT_CUT, 2)
define amdgpu_kernel void @test_gs_emit_cut() {
body:
call void @llvm.amdgcn.s.sendmsg(i32 562, i32 0)
ret void
}
; GCN-LABEL: {{^}}test_gs_done:
; GCN: s_mov_b32 m0, 0
; GCN-NOT: s_mov_b32 m0
; GCN: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)
define amdgpu_kernel void @test_gs_done() {
body:
call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
ret void
}
; GCN-LABEL: {{^}}test_gs_alloc_req:
; GCN: s_mov_b32 m0, s0
; GCN-NOT: s_mov_b32 m0
; VIPLUS-NEXT: s_nop 0
; SIVI: s_sendmsg sendmsg(9, 0, 0)
; GFX9: s_sendmsg sendmsg(MSG_GS_ALLOC_REQ)
define amdgpu_kernel void @test_gs_alloc_req(i32 inreg %a) {
body:
call void @llvm.amdgcn.s.sendmsg(i32 9, i32 %a)
ret void
}
; GCN-LABEL: {{^}}sendmsg:
; GCN: s_mov_b32 m0, s0
; VIPLUS-NEXT: s_nop 0
; GCN-NEXT: sendmsg(MSG_GS_DONE, GS_OP_NOP)
; GCN-NEXT: s_endpgm
define amdgpu_gs void @sendmsg(i32 inreg %a) #0 {
call void @llvm.amdgcn.s.sendmsg(i32 3, i32 %a)
ret void
}
; GCN-LABEL: {{^}}sendmsghalt:
; GCN: s_mov_b32 m0, s0
; VIPLUS-NEXT: s_nop 0
; GCN-NEXT: s_sendmsghalt sendmsg(MSG_INTERRUPT)
; GCN-NEXT: s_endpgm
define amdgpu_kernel void @sendmsghalt(i32 inreg %a) #0 {
call void @llvm.amdgcn.s.sendmsghalt(i32 1, i32 %a)
ret void
}
; GCN-LABEL: {{^}}test_interrupt_halt:
; GCN: s_mov_b32 m0, 0
; GCN-NOT: s_mov_b32 m0
; GCN: s_sendmsghalt sendmsg(MSG_INTERRUPT)
define amdgpu_kernel void @test_interrupt_halt() {
body:
call void @llvm.amdgcn.s.sendmsghalt(i32 1, i32 0)
ret void
}
; GCN-LABEL: {{^}}test_gs_emit_halt:
; GCN: s_mov_b32 m0, 0
; GCN-NOT: s_mov_b32 m0
; GCN: s_sendmsghalt sendmsg(MSG_GS, GS_OP_EMIT, 0)
define amdgpu_kernel void @test_gs_emit_halt() {
body:
call void @llvm.amdgcn.s.sendmsghalt(i32 34, i32 0)
ret void
}
; GCN-LABEL: {{^}}test_gs_cut_halt:
; GCN: s_mov_b32 m0, 0
; GCN-NOT: s_mov_b32 m0
; GCN: s_sendmsghalt sendmsg(MSG_GS, GS_OP_CUT, 1)
define amdgpu_kernel void @test_gs_cut_halt() {
body:
call void @llvm.amdgcn.s.sendmsghalt(i32 274, i32 0)
ret void
}
; GCN-LABEL: {{^}}test_gs_emit_cut_halt:
; GCN: s_mov_b32 m0, 0
; GCN-NOT: s_mov_b32 m0
; GCN: s_sendmsghalt sendmsg(MSG_GS, GS_OP_EMIT_CUT, 2)
define amdgpu_kernel void @test_gs_emit_cut_halt() {
body:
call void @llvm.amdgcn.s.sendmsghalt(i32 562, i32 0)
ret void
}
; GCN-LABEL: {{^}}test_gs_done_halt:
; GCN: s_mov_b32 m0, 0
; GCN-NOT: s_mov_b32 m0
; GCN: s_sendmsghalt sendmsg(MSG_GS_DONE, GS_OP_NOP)
define amdgpu_kernel void @test_gs_done_halt() {
body:
call void @llvm.amdgcn.s.sendmsghalt(i32 3, i32 0)
ret void
}
; GCN-LABEL: {{^}}test_mul24:
; GCN: s_and_b32 s0, s0, 0x1ff
; GCN: s_mul_i32 m0, s0, 0x3000
; GCN: s_sendmsg sendmsg(MSG_INTERRUPT)
define amdgpu_gs void @test_mul24(i32 inreg %arg) {
body:
%tmp1 = and i32 %arg, 511
%tmp2 = mul nuw nsw i32 %tmp1, 12288
call void @llvm.amdgcn.s.sendmsg(i32 1, i32 %tmp2)
ret void
}
; GCN-LABEL: {{^}}if_sendmsg:
; GCN: s_cbranch_execz
; GCN: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)
define amdgpu_gs void @if_sendmsg(i32 %flag) #0 {
%cc = icmp eq i32 %flag, 0
br i1 %cc, label %sendmsg, label %end
sendmsg:
call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
br label %end
end:
ret void
}
declare void @llvm.amdgcn.s.sendmsg(i32, i32) #0
declare void @llvm.amdgcn.s.sendmsghalt(i32, i32) #0
attributes #0 = { nounwind }
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