116c894d72
AMDGPU legalizes i64 loads to loads of <2 x i32>, leaving the i64 MMO with attached range metadata alone. The known bit width was using the scalar element type, and asserting on a mismatch.
35 lines
1.4 KiB
LLVM
35 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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define <2 x i32> @range_metata_sext_range_0_i24_i64_bitcast(ptr addrspace(1) %ptr) {
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; GCN-LABEL: range_metata_sext_range_0_i24_i64_bitcast:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: global_load_dwordx2 v[0:1], v[0:1], off glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%val = load volatile i64, ptr addrspace(1) %ptr, align 4, !range !0
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%shl = shl i64 %val, 22
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%ashr = ashr i64 %shl, 22
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%cast = bitcast i64 %ashr to <2 x i32>
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ret <2 x i32> %cast
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}
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define <2 x i32> @no_range_sext_range_0_i24_i64_bitcast(ptr addrspace(1) %ptr) {
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; GCN-LABEL: no_range_sext_range_0_i24_i64_bitcast:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: global_load_dwordx2 v[0:1], v[0:1], off glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_lshlrev_b64 v[0:1], 22, v[0:1]
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; GCN-NEXT: v_ashrrev_i64 v[0:1], 22, v[0:1]
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%val = load volatile i64, ptr addrspace(1) %ptr, align 4
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%shl = shl i64 %val, 22
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%ashr = ashr i64 %shl, 22
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%cast = bitcast i64 %ashr to <2 x i32>
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ret <2 x i32> %cast
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}
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!0 = !{i64 0, i64 16777216}
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