241 lines
9.1 KiB
LLVM
241 lines
9.1 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GFX89 %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX89 %s
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone speculatable
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; GCN-LABEL: {{^}}s_sub_i32:
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; GCN: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}]
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; GCN: s_sub_i32 s{{[0-9]+}}, s[[#LOAD + 2]], s[[#LOAD + 3]]
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define amdgpu_kernel void @s_sub_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {
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%result = sub i32 %a, %b
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}s_sub_imm_i32:
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; GCN: s_load_dword [[A:s[0-9]+]]
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; GCN: s_sub_i32 s{{[0-9]+}}, 0x4d2, [[A]]
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define amdgpu_kernel void @s_sub_imm_i32(ptr addrspace(1) %out, i32 %a) {
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%result = sub i32 1234, %a
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_sub_i32:
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; SI: v_subrev_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
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; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define amdgpu_kernel void @test_sub_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%b_ptr = getelementptr i32, ptr addrspace(1) %in, i32 1
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%a = load i32, ptr addrspace(1) %in
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%b = load i32, ptr addrspace(1) %b_ptr
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%result = sub i32 %a, %b
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_sub_imm_i32:
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc, 0x7b, v{{[0-9]+}}
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; GFX9: v_sub_u32_e32 v{{[0-9]+}}, 0x7b, v{{[0-9]+}}
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define amdgpu_kernel void @test_sub_imm_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%a = load i32, ptr addrspace(1) %in
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%result = sub i32 123, %a
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_sub_v2i32:
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; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
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; SI: v_subrev_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
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; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define amdgpu_kernel void @test_sub_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%b_ptr = getelementptr <2 x i32>, ptr addrspace(1) %in, i32 1
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%a = load <2 x i32>, ptr addrspace(1) %in
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%b = load <2 x i32>, ptr addrspace(1) %b_ptr
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%result = sub <2 x i32> %a, %b
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store <2 x i32> %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_sub_v4i32:
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; SI: v_subrev_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
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; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
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; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
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; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
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; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define amdgpu_kernel void @test_sub_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%b_ptr = getelementptr <4 x i32>, ptr addrspace(1) %in, i32 1
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%a = load <4 x i32>, ptr addrspace(1) %in
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%b = load <4 x i32>, ptr addrspace(1) %b_ptr
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%result = sub <4 x i32> %a, %b
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store <4 x i32> %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_sub_i16:
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
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; GFX89: v_sub_u16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define amdgpu_kernel void @test_sub_i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i16, ptr addrspace(1) %in, i32 %tid
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%b_ptr = getelementptr i16, ptr addrspace(1) %gep, i32 1
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%a = load volatile i16, ptr addrspace(1) %gep
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%b = load volatile i16, ptr addrspace(1) %b_ptr
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%result = sub i16 %a, %b
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store i16 %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_sub_v2i16:
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; VI: v_sub_u16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; VI: v_sub_u16_sdwa v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX9: v_pk_sub_i16
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define amdgpu_kernel void @test_sub_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr <2 x i16>, ptr addrspace(1) %in, i32 %tid
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%b_ptr = getelementptr <2 x i16>, ptr addrspace(1) %gep, i16 1
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%a = load <2 x i16>, ptr addrspace(1) %gep
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%b = load <2 x i16>, ptr addrspace(1) %b_ptr
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%result = sub <2 x i16> %a, %b
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store <2 x i16> %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_sub_v4i16:
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; VI: v_sub_u16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; VI: v_sub_u16_sdwa v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; VI: v_sub_u16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; VI: v_sub_u16_sdwa v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX9: v_pk_sub_i16
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; GFX9: v_pk_sub_i16
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define amdgpu_kernel void @test_sub_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr <4 x i16>, ptr addrspace(1) %in, i32 %tid
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%b_ptr = getelementptr <4 x i16>, ptr addrspace(1) %gep, i16 1
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%a = load <4 x i16>, ptr addrspace(1) %gep
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%b = load <4 x i16>, ptr addrspace(1) %b_ptr
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%result = sub <4 x i16> %a, %b
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store <4 x i16> %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}s_sub_i64:
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; GCN: s_sub_u32
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; GCN: s_subb_u32
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define amdgpu_kernel void @s_sub_i64(ptr addrspace(1) noalias %out, i64 %a, i64 %b) nounwind {
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%result = sub i64 %a, %b
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store i64 %result, ptr addrspace(1) %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}v_sub_i64:
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; SI: v_sub_i32_e32
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; SI: v_subb_u32_e32
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; VI: v_sub_u32_e32
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; VI: v_subb_u32_e32
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; GFX9: v_sub_co_u32_e32
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; GFX9: v_subb_co_u32_e32
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define amdgpu_kernel void @v_sub_i64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %inA, ptr addrspace(1) noalias %inB) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() readnone
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%a_ptr = getelementptr i64, ptr addrspace(1) %inA, i32 %tid
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%b_ptr = getelementptr i64, ptr addrspace(1) %inB, i32 %tid
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%a = load i64, ptr addrspace(1) %a_ptr
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%b = load i64, ptr addrspace(1) %b_ptr
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%result = sub i64 %a, %b
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store i64 %result, ptr addrspace(1) %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}v_test_sub_v2i64:
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
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; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
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; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc,
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define amdgpu_kernel void @v_test_sub_v2i64(ptr addrspace(1) %out, ptr addrspace(1) noalias %inA, ptr addrspace(1) noalias %inB) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() readnone
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%a_ptr = getelementptr <2 x i64>, ptr addrspace(1) %inA, i32 %tid
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%b_ptr = getelementptr <2 x i64>, ptr addrspace(1) %inB, i32 %tid
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%a = load <2 x i64>, ptr addrspace(1) %a_ptr
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%b = load <2 x i64>, ptr addrspace(1) %b_ptr
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%result = sub <2 x i64> %a, %b
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store <2 x i64> %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}v_test_sub_v4i64:
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
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; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
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; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
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; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
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; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc,
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define amdgpu_kernel void @v_test_sub_v4i64(ptr addrspace(1) %out, ptr addrspace(1) noalias %inA, ptr addrspace(1) noalias %inB) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() readnone
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%a_ptr = getelementptr <4 x i64>, ptr addrspace(1) %inA, i32 %tid
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%b_ptr = getelementptr <4 x i64>, ptr addrspace(1) %inB, i32 %tid
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%a = load <4 x i64>, ptr addrspace(1) %a_ptr
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%b = load <4 x i64>, ptr addrspace(1) %b_ptr
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%result = sub <4 x i64> %a, %b
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store <4 x i64> %result, ptr addrspace(1) %out
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ret void
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}
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; Make sure the VOP3 form of sub is initially selected. Otherwise pair
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; of opies from/to VCC would be necessary
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; GCN-LABEL: {{^}}sub_select_vop3:
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; SI: v_subrev_i32_e64 v0, s[0:1], s0, v0
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; VI: v_subrev_u32_e64 v0, s[0:1], s0, v0
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; GFX9: v_subrev_u32_e32 v0, s0, v0
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; GCN: ; def vcc
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; GCN: ds_write_b32
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; GCN: ; use vcc
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define amdgpu_ps void @sub_select_vop3(i32 inreg %s, i32 %v) {
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%vcc = call i64 asm sideeffect "; def vcc", "={vcc}"()
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%sub = sub i32 %v, %s
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store i32 %sub, ptr addrspace(3) undef
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call void asm sideeffect "; use vcc", "{vcc}"(i64 %vcc)
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ret void
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}
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